[USRP-users] Re: How can solve this error in RFNOC: RfnocError: ResolveError: Attempting to overwrite property `freq@USER:0'

2023-12-24 Thread sp
My problem is solved this error is related to uhd version I changed uhd 4.2.0 to 4.1.0 now my rfnoc block works like charm. On Fri, Dec 22, 2023 at 4:58 PM sp wrote: > When I want to use RFNOC block in USRP I am faced with errors.How can > solve it? can anyone help? thanks in a

[USRP-users] How can solve this error in RFNOC: RfnocError: ResolveError: Attempting to overwrite property `freq@USER:0'

2023-12-22 Thread sp
`freq@USER:0' with a new value after it > was locked! > Traceback (most recent call last): > File "/home/sp/Downloads/rfnoc45.py", line 211, in > main() > File "/home/sp/Downloads/rfnoc45.py", line 189, in main > tb.start() > File "/usr

[USRP-users] what's default spp in a rfnoc blocks? how can set spp in testbench to 1?

2023-09-28 Thread sp
I want to when i examine rfnoc block or example blocks spp is set to 64 in the test bench, my question is in FPGA what's the spp default for ordinary blocks? I need spp to be 1 , but when I changed it I faced a strange error and the simulation has an error Fatal: ChdrIfaceBfm::set_max_payload_leng

[USRP-users] Re: Failure: ERROR:add_1 must be in range [-1,DEPTH-1]

2023-09-12 Thread sp
ut_tdata), // I .m_axis_dout_tlast (signal_out_tlast), .m_axis_dout_tvalid (sinal_out_tvalid), .m_axis_dout_tready (signal_out_tready) ); On Sat, Sep 9, 2023 at 4:32 PM sp wrote: > When I added this section a CORDIC IPCORE to rfnoc gain block I faced a > strange error Failure: ERROR:add_1 must be in

[USRP-users] Failure: ERROR:add_1 must be in range [-1,DEPTH-1]

2023-09-09 Thread sp
When I added this section a CORDIC IPCORE to rfnoc gain block I faced a strange error Failure: ERROR:add_1 must be in the range [-1,DEPTH-1] How can solve this error? Anyone can guide me? wire [15:0] phase_out_tdata; wire phase_out_tvalid; wire phase_out_tready; wire [31:0] sine_out_tdata; wire s

[USRP-users] Re: Fatal: Timeout: Test "Test passing through samples" time limit exceeded

2023-08-23 Thread sp
d why. You can of course remove the timeout, but that > won't necessarily fix the problem. > > Wade > > On Tue, Aug 22, 2023 at 12:55 AM sp wrote: > >> I write a custom block when i run test bench on it i faced with strange >> error,How can solve it i share

[USRP-users] Re: why $diplay function is not work in my custom rfnoc block but

2023-08-21 Thread sp
rget that the $display > function is only used for simulation, but not synthesis. Therefore; it is > best to use it in testbench files. > > Kind Regards, > Yasir > > sp , 22 Ağu 2023 Sal, 08:48 tarihinde şunu > yazdı: > >> Thanks very much, simulation test bench sv fil

[USRP-users] Fatal: Timeout: Test "Test passing through samples" time limit exceeded

2023-08-21 Thread sp
CASE 4] (t = 7725 ns) BEGIN: Test passing through samples... Fatal: Timeout: Test "Test passing through samples" time limit exceeded Time: 17725 ns Iteration: 0 Process: /PkgTestExec/TestExec::start_timeout/Block260_9/timeout File: /home/sp/Documents/uhd-4.1.0.5/fpga/usrp3

[USRP-users] why $diplay function is not work in my custom rfnoc block but

2023-08-21 Thread sp
why $diplay function is not work in my custom rfnoc block but it work in other rfnoc blocks on usrp, How can solve my problem? I know that with rfnoc framework $diplay should be work in rfnoc blocks but every thing is same other block only name of block is diff... thanks in advance

[USRP-users] Re: How can add some verilog dir file to rfnoc block make file

2023-08-14 Thread sp
instance [/home/sp/rfnoc-test/rfnoc /fpga/rfnoc_block_gain/correlate.v:132] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/sp/rfnoc-test/rfnoc /fpga/rfnoc_block_gain/correlate.v:164] How am I adding non-ip core to my custom module. I added a make file and

[USRP-users] How can add some verilog dir file to rfnoc block make file

2023-08-12 Thread sp
[/home/sp/rfnoc-test/rfnoc/fpga/rfnoc_block_gain/correlate.v:132] ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/sp/rfnoc-test/rfnoc/fpga/rfnoc_block_gain/correlate.v:164] #- # Top-of-Makefile

[USRP-users] how to run multiple jobs in rfnoc image build for usrp with xilinx....

2023-08-01 Thread sp
in xilinx vivado and ise design suite in gui project when i want to build project there is a option that we can select number of jobs for builds how can we set number of job for building rfnoc blocks and image of usrp for building we use rfnoc image builder but i can not see any number of jobs

[USRP-users] Re: error in installing nuradio 3.8 with UHD4.2.0

2023-06-19 Thread sp
Thanks very much a UHD old header file caused this problem i remove them now it works. On Tue, Jun 20, 2023 at 10:22 AM Marcus Müller wrote: > Dear sp, > > the GNU Radio mailing list couldn't solve it because we asked for line > numbers and > verbatim error messages[1], b

[USRP-users] error in installing nuradio 3.8 with UHD4.2.0

2023-06-19 Thread sp
/uhd_swigPYTHON_wrap.cxx.o [ 51%] Building CXX object gr-blocks/lib/CMakeFiles/gnuradio-blocks.dir/stream_to_streams_impl.cc.o /home/sp/Documents/gnuradio/build/gr-uhd/swig/CMakeFiles/uhd_swig.dir/uhd_swigPYTHON_wrap.cxx: In function ‘PyObject* _wrap_dboard_iface_sleep(PyObject*, PyObject*, PyObject

[USRP-users] What is delay change frequency USRP daughterboard when i used PCIe vs Ethernet?

2023-06-17 Thread sp
What is the delay change frequency USRP daughterboard when I used PCIe vs Ethernet? I have a USRP x310, and when I send a change frequency to change the frequency it takes long .2 ms, this delay is for the ethernet command sent to the daughterboard I measure it with cpp code, but I had not any PCIe

[USRP-users] How I can chagne RFNOC blocks to another daughter board or RF B?

2023-02-28 Thread sp
I simulated an RX RFNOC block as a receiver, it works correctly but I want to RX RFNOC blocks to be executed on RF B or another daughter board. how can change it to another daughter board... Thanks very much. ___ USRP-users mailing list -- usrp-users@list

[USRP-users] How many user reg we can define in a RFNOC block?

2022-11-14 Thread sp
I have developed some RFNOC blocks. I had a question. in an RFNOC block HOW many user registers can we use? can we use three user reg in a RFNOC blocks? Thanks in advance ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an ema

[USRP-users] Re: Why when I changed inputs of RFNOC blocks it is not changed in file x300_rfnoc_image_core.v

2022-11-10 Thread sp
Hi, My problem is solved. By adding the option -n I force rfnoc_image_builder to use that image core that I define it. rfnoc_image_builder-n /home/sp/rfnoc-test/rfnoc/icores/x300_rfnoc_image_core2.v On Thu, Nov 10, 2022 at 6:01 AM sp wrote: > I used an RFNOC gain example file when I w

[USRP-users] Why when I changed inputs of RFNOC blocks it is not changed in file x300_rfnoc_image_core.v

2022-11-09 Thread sp
I used an RFNOC gain example file when I want to change the input of the gain block as below... module rfnoc_block_gain #( parameter [9:0] THIS_PORTID = 10'd0, parameter CHDR_W = 64, parameter [5:0] MTU = 10, parameter NUM_PORTS = 1 )( // R

[USRP-users] Re: How can I define a global reg variable in Verilog between RFNOC blocks?

2022-11-08 Thread sp
Thanks very much, Marcus. Can explain more? I had not any idea how develop your way? On Mon, Nov 7, 2022 at 11:29 PM Marcus Müller wrote: > Hi sp, > > That sounds like a bad idea. How are you planning to synchronize access to > that register? > > Generally, in almost *any* con

[USRP-users] Re: How can I define a global reg variable in Verilog between RFNOC blocks?

2022-11-07 Thread sp
; > new port on the noc_block > > 4. Now you can manage the (shared) reg variable from inside the noc block. > > Hope this can be of some help. > > Have a good day, > > paolo > > On 7/31/22 17:52, sp wrote: > > How can I define a global reg variable in Veril

[USRP-users] How can we develop two RFNOC block that there is a reg relation between them?

2022-11-06 Thread sp
I am developing two RFNOC blocks, a gain block, and a multiplier block... But I need there to be a reg relation between RFNOC blocks... for example, a multiply_const is calculated in multiply rfnoc block and it is used to block gain... when I add the reg in rfnoc block and I define it as input and

[USRP-users] what's means device select and instance select in RFNOC blocks?

2022-11-03 Thread sp
what's the mean device select and instance select in RFNOC blocks? they are vague for me? can anyone guide me? [image: Screenshot from 2022-11-03 18-12-37.png] ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-

[USRP-users] when I intialize block RAM and I want to use block RAM in a FOR I faced with this invalid memory name?

2022-10-22 Thread sp
tdata, output o_tlast, output o_tvalid, input o_tready); reg signed [15:0] data_samples_i_buffer [1024:0]; reg signed [15:0] data_samples_q_buffer [1024:0]; reg [31:0] edgei_tbl_rom[0:1024]; reg [31:0] edgeq_tbl_rom[0:1024]; initial begin //Initial $readmemh("/home/sp/rfnoc-test/

[USRP-users] Re: Why initialize large array in Verilog is not successfully in RFNOC blocks...

2022-10-22 Thread sp
]; reg [31:0] edgeq_tbl_rom[0:1024]; initial begin //Initial $readmemh("/home/sp/rfnoc-test/rfnoc/fpga/rfnoc_block_multiplier/1.hex" ,edgei_tbl_rom,0,1024); $readmemh("/home/sp/rfnoc-test/rfnoc/fpga/rfnoc_block_multiplier/1.hex" ,edgeq_tbl_rom,0,1024); ebd always @(posedge conf

[USRP-users] Re: Why initialize large array in Verilog is not successfully in RFNOC blocks...

2022-10-15 Thread sp
; > > On Thu, Oct 13, 2022, 7:39 AM sp wrote: > >> Why initialize large array in Verilog is not successfully. When size of >> array is 255 it work like charm but for other number more than 255 like >> 1024 and >> we observe all array is filled with zero? why l

[USRP-users] Why initialize large array in Verilog is not successfully in RFNOC blocks...

2022-10-13 Thread sp
Why initialize large array in Verilog is not successfully. When size of array is 255 it work like charm but for other number more than 255 like 1024 and we observe all array is filled with zero? why large array in FPGA can not initailize correctly Code: reg signed [15:0] data_i_patter

[USRP-users] Re: [RFNOC::BLOCK_FACTORY] Could not find block with Noc-ID 0x2cd7049b, 0xffff

2022-08-30 Thread sp
>> use rfnoc-example, name of the file should be different) >> If you call this in terminal before uhd_usrp_probe, then you should not >> see that warning. >> >> Yasir >> >> sp , 29 Ağu 2022 Pzt, 15:03 tarihinde şunu >> yazdı: >> >>>

[USRP-users] [RFNOC::BLOCK_FACTORY] Could not find block with Noc-ID 0x2cd7049b, 0xffff

2022-08-29 Thread sp
When I built FPGA for RFNOC block I faced with strange error...I check the FPGA source and RFNOC CPP source every id is ok but my code doesn't work correctly... Can any help me? uhd_usrp_probe [INFO] [UHD] linux; GNU C++ version 9.4.0; Boost_107100; UHD_4.2.0.0-0-unknown [INFO] [X300] X300 ini

[USRP-users] How can I define a global reg variable in Verilog between RFNOC blocks?

2022-07-31 Thread sp
How can I define a global reg variable in Verilog between RFNOC blocks? I developed two RFNOC blocks: RFNOC block A, and RFNOC block B How can define a reg variable that shares between RFNOC blocks in USRP? Can anyone guide me? I study about global reg variable in the Verilog module, see below lin

[USRP-users] Re: How use convert class in UHD to convert complex float to complex sint16?

2022-07-09 Thread sp
Ok, thanks for the clarification. On Sat, Jul 9, 2022 at 9:15 PM Marcus D. Leech wrote: > On 2022-07-09 12:40, sp wrote: > > Marcus D. Leech thanks very much. Your description is very useful for me. > But I am not a communication engineer, I am a software developer, Can you > in

[USRP-users] Re: How use convert class in UHD to convert complex float to complex sint16?

2022-07-09 Thread sp
Python program to re-scale it. of course in helping a communication engineer. On Sat, Jul 9, 2022 at 8:57 PM Marcus D. Leech wrote: > On 2022-07-09 12:01, sp wrote: > > I assume this already does ceil or floor, so your data needs to be >> already in the right scale:) >> >

[USRP-users] Re: How use convert class in UHD to convert complex float to complex sint16?

2022-07-09 Thread sp
> > I assume this already does ceil or floor, so your data needs to be > already in the right scale:) > But all of my problems are related to scaling... want to use the converted class in USRP that can solve my scaling problem and I am sure that my data is converted correctly.. So I want to use on

[USRP-users] How use convert class in UHD to convert complex float to complex sint16?

2022-07-09 Thread sp
I know that data in USRP on FPGA is in format big-endian sint16, but in Gnuradio data is in format complex float 32... I found these links The conversion encompasses several elements. The most obvious is that of the data type: Most FPGAs use integer data types, the most common being complex 16-bit

[USRP-users] Re: How can convert a complex float 32 signal to complex int 16 signal for using in USRP??

2022-07-06 Thread sp
Thanks! I will examine your useful description... On Sun, Jul 3, 2022 at 8:45 PM Marcus D. Leech wrote: > On 2022-07-03 11:29, sp wrote: > > Thanks! So I set scaler to an appropriate value that ceil is not > effected my data. But in Gnuradio I can not find an easy convert solutio

[USRP-users] Re: How can convert a complex float 32 signal to complex int 16 signal for using in USRP??

2022-07-03 Thread sp
float to int, you always have to ceil or floor the > float. > > > Ceil sounds as good as any. You can easily change that to floor if you > > > run into problems. > > > Since clibs le32to* take ints as arguments, I would first convert > > > float32 to int32 from gnuradi

[USRP-users] How can convert a complex float 32 signal to complex int 16 signal for using in USRP??

2022-06-30 Thread sp h
I recorded a complex signal file, I did it with HackRFONE, For sending on USRP I want to use the int16 option as input, My question is how can convert a complex float 32 signal to complex int 16 for USRP? what's the relation between complex float 32 and complex int 32 in USRP? I know that in USRP

[USRP-users] Re: Why RFNOC gain example building FPGA, I faced with module 'rfnoc_block_gain' not found?

2022-06-22 Thread sp h
RFNOC block folder and I was faced with error not found... > makefile_srcs: > "${fpga_lib_dir}/blocks/rfnoc_block_correlate/Makefile.srcs" On Wed, Jun 22, 2022 at 12:53 PM sp h wrote: > Finally, I mention that, I found there is a bug in UHD 4.1.0.5 or UHD > 4.2.0.0 when

[USRP-users] Re: Error in building USRP FPGA bitstream module 'rfnoc_block_fft' not found

2022-06-22 Thread sp h
RFNOC block folder and I was faced with error not found... > makefile_srcs: > "${fpga_lib_dir}/blocks/rfnoc_block_correlate/Makefile.srcs" On Sun, Feb 13, 2022 at 10:39 AM sp h wrote: > Finally, I edited the RFNOC image core when I used the default RFNOC > image core x30

[USRP-users] Re: TwinRX daughterboard is the only a receiver...but for it Transmit mode works and led red is on, is it a bug???!!!!!

2022-06-20 Thread sp h
DAC to the TwinRx. > > Sent from my iPhone > > > On Jun 19, 2022, at 9:44 PM, sp h wrote: > > > >  > > I have a daughterboard TwinRX in RF B in x300. When I use UHD and set > the stream channel to 1 . > > as TwinRX daughterboard is the only receive

[USRP-users] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license In building FPGA UHD 4.2.0.0

2022-06-16 Thread sp h
When I want to build UHD 4.2.0.0 I faced with below warning. > IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a > Design_Linking license. Building FPGA process cannot go to compile other IP cores and stays in ten_gig_eth_pcs_pma IP and repeats... For UHD v4.1.0.5 I had no p

[USRP-users] Re: When I added ce clock domain to RFNOC gain block and I synthesized it, in Gnuradio it generates OOOO

2022-06-16 Thread sp h
I examine all of the code again and again but my problem is not solved yet... any RFNOC developer can not guide me? thanks in advance On Tue, Jun 14, 2022 at 11:21 AM sp h wrote: > When I added ce clock domain to gain block and synthesized it, in Gnuradio > it generates > I at

[USRP-users] Re: Is it possible that synthesis and generating bitstream in RFNOC blocks make faster??!!!

2022-06-14 Thread sp h
Thanks for the feedback! I will test them. On Tue, Jun 14, 2022 at 1:42 AM Wade Fife wrote: > Hi sp, > > It is possible to use incremental implementation using the checkpoints > generated by the build flow, but I've never tried it with USRPs. This is an > advanced Vivado

[USRP-users] When I added ce clock domain to RFNOC gain block and I synthesized it, in Gnuradio it generates OOOO

2022-06-13 Thread sp h
When I added ce clock domain to gain block and synthesized it, in Gnuradio it generates I attached my source code in below, can anyone guide me? I emphasize that I read the RFNOC FFT and replay blocks and according to them, I added ce clocks... FFT and replay block work successfully but for t

[USRP-users] Is it possible that synthesis and generating bitstream in RFNOC blocks make faster??!!!

2022-06-12 Thread sp h
: > rfnoc_image_builder -F /home/sp/Documents/uhd-4.1.0.5/fpga -I > /home/sp/Documents/rfnoc-module -p /home/sp/xilinx/Vivado -y > /home/sp/Documents/rfnoc-module/rfnoc/icores/gain_x300_rfnoc_image_core.yml My question is there any option that makes RFNOC synthesis faster? like in

[USRP-users] Re: How to add an ip core to rfnoc OOT block

2022-06-06 Thread sp h
path (/home/sp/Documents/uhd-4.2.0.0/fpga/usrp3/lib ) exist a folder as name ip.. IP cores that we need should be defined in the UHD driver folder... Your IP list should be added to this folder and changed makefiles carefully Before you complete your development may be useful this info that we f

[USRP-users] Re: How to add an ip core to rfnoc OOT block

2022-06-05 Thread sp h
Hi, You should not expect that integrate or add Xilinx IP core directly to RFNOC blocks, Even If you be a master in Verilog... If you see the UHD source code you will realize that UHD is an RFNOC framework for USRP ... For working with the RFNOC UHD framework you should know more details: 1)Please

[USRP-users] Re: What's RFNOC image builder Unit in gr-ettus and Gnuradio?

2022-05-29 Thread sp h
:46 PM sp h wrote: > Yes, I read all UHD 4 Docs and GRCON videos but do these blocks in image > builder really work? I think they are not stable and have a bug ... > Does anyone work with them? ... So I manually change the USRP image core. > But in GUI I had ambiguity... So I ask. &

[USRP-users] When I want to customize RFNOC blocks, like adding FFT block in Gnuradio generate OOOOOOOOOOO?

2022-05-27 Thread sp h
When I want to customize RFNOC blocks, like adding an FFT block in Gnuradio generate OOO? When I change the RFNOC image core in USRP from the below link, the FFT block does not work in Gnuradio, For the Gain block same problem... https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0

[USRP-users] What's means letters and numbers 0/RFNOCSection#X:X in SEP and RFNOC connections?

2022-05-24 Thread sp h
when I used uhd_usrp_probe it returns the RFNOC block list and static connections between them. my question is what's means numbers in them? can anyone guide me? I know that #X should be the numeric id of the RFNOC block... I think number two is the number port? wich port is input wich is output?

[USRP-users] Re: What's means ce_clk in orginal USRP blocks? as it is not in rfnoc-example ....

2022-05-22 Thread sp h
videos: Exploring RFNoC 4 with the UHD Python API - > https://youtu.be/fbcxm7f-Tj0 > <https://www.youtube.com/watch?v=fbcxm7f-Tj0&t=0s> RFNoC 3 workshop video > - https://youtu.be/VbODcrmpLaU > <https://www.youtube.com/watch?v=VbODcrmpLaU&t=0s> > > Hope this helps,

[USRP-users] What's means ce_clk in orginal USRP blocks? as it is not in rfnoc-example ....

2022-05-21 Thread sp h
when I examine RFNOC block that is in the below path, I am faced with a wire ce_clk and ce_rst, but in rfnoc-example there is not a ce_clk. uhd-4.1.0.5/fpga/usrp3/lib/rfnoc/blocks Can anyone guide me ce clocks? why instead using rfnoc_chdr clk, original blocks uses ce clock?

[USRP-users] Clock incompatibility in UHD example UHD-4.1.0.5,Can any developer examine it?

2022-05-21 Thread sp h
] Starting Synthesis Command ERROR: [Synth 8-448] named port connection 'ce_clk' does not exist for instance 'b_gain0_6' of module 'rfnoc_block_gain' [/home/sp/Documents/rfnoc-transceiver/rfnoc/icores/x300_rfnoc_image_core.v:1058] ERROR: [Synth 8-6156] failed synthesi

[USRP-users] Is it possible that I changed center frequency and gain of USRP from the Verilog code (In a RFNOC block)?

2022-05-10 Thread sp h
Is it possible that I changed center frequency and gain of USRP from the Verilog code? I study API CPP Gnuradio and UHD, In CPP we can change the frequency and gain of USRP easily ... But for me there is a question can I change the frequency or gain USRP from Verilog in an RFNOC block? Thanks in a

[USRP-users] ValueError: Bad CHDR header or invalid packet length

2022-05-10 Thread sp h
I developed an RFNOC block for USRP x300, When I want to test it in Gnuradio, the block does not work and I am faced with the below errors ... How can solve my problem? I mention that it has a critical warning in synthesis ...This warning is below link: https://lists.ettus.com/empathy/thread/7HN6J

[USRP-users] What's means this warning, CRITICAL WARNING: [Constraints 18-1056] Clock 'FPGA_CLK' completely overrides clock 'FPGA_CLK_p'.

2022-04-29 Thread sp h
In the body of an RFNOC block code, I had a for in for and calculation but when I want to synthesize it I was faced with a clock warning in FPGA. When I comment on this section this error is disappeared... So when I used a delay with tag # in some cases warning is removed... I:Errors: [00:04:49] C

[USRP-users] Re: How can debug [00:04:42] Process terminated. Status: Failure

2022-04-29 Thread sp h
he code in your RFNoC > block and gradually uncomment it until you can narrow down what section of > code is causing Vivado to fail. Hopefully you can narrow down which > statement is the cause. When you run the build, monitor the memory usage to > make sure that's not an issue. > &

[USRP-users] Re: Why include a Verilog file not work in the RFNOC block?

2022-04-19 Thread sp h
Ok, thanks. My problem is solved. On Tue, Apr 19, 2022 at 5:29 AM Wade Fife wrote: > Hi sp, > > You can include files. It looks like you misspelled "correlate" (the error > says 'corrleate.vh'). Also, if the file is not in the same folder as > rfnoc_bloc

[USRP-users] Why include a Verilog file not work in the RFNOC block?

2022-04-18 Thread sp h
Why include a Verilog file not work in the RFNOC block? In Verilog, we can include another file in the source Verilog file, but when I did in an RFNOC block I faced errors... can you any offers? ERROR: [VRFC 10-3195] cannot open include file 'corrleate.vh' [rfnoc/rfnoc/fpga/rfnoc_block_correlate/r

[USRP-users] Re: Error: Incorrect NOC_ID Value in creating new RFNOC block

2022-04-16 Thread sp h
Finally, my problem is solved... NOC_ID value in .sv file and noc_shell file should be same.Otherwise, you will face erros... On Sun, Apr 17, 2022 at 10:01 AM sp h wrote: > Hi, when I changed the name of the Gain block to another name, I want to > run the test bench and simulated it but

[USRP-users] Error: Incorrect NOC_ID Value in creating new RFNOC block

2022-04-16 Thread sp h
Process: /rfnoc_block_correlate_tb/Initial172_431 File: /home/sp/Documents/rfnoc-transceiver/rfnoc/fpga/rfnoc_block_correlate/ rfnoc_block_correlate_tb.sv $stop called at time : 6450 ns : File "/home/sp/Documents/rfnoc-transceiver/rfnoc/fpga/rfnoc_block_correlate/ rfnoc_block_correlate_tb.sv"

[USRP-users] Re: When I run the gain example testbench file I am faced with errors.....

2022-04-05 Thread sp h
ions on how to run testbenches and load the > simulation in the Vivado GUI. > > My guess is that you have a signal that's not connected correctly, like a > clock or reset. > > Wade > > On Tue, Apr 5, 2022 at 12:42 AM sp h wrote: > >> When I run the gain examp

[USRP-users] When I run the gain example testbench file I am faced with errors.....

2022-04-04 Thread sp h
[TEST CASE 1] (t = 0 ns) BEGIN: Flush block then reset it... *Fatal: Timeout: Test "Flush block then reset it" time limit exceeded*Time: 10 us Iteration: 0 Process: /PkgTestExec/TestExec::start_timeout/Block260_9/timeout File: /home/sp/Doc

[USRP-users] Re: Default CHDR_W is 64 for a RFNOC blocks, How can increased samples buffer in RFNOC block to 4096...

2022-03-21 Thread sp h
:01 PM sp h wrote: > But I need to add samples to a buffer. when 4096 sample is received for > block, do an operation like correlate and convolution, and so on. > > Can we use RAM in an RFNOC block that enables us to work with specific > count samples?? > It is possible? > &

[USRP-users] Default CHDR_W is 64 for a RFNOC blocks, How can increased samples buffer in RFNOC block to 4096...

2022-03-21 Thread sp h
Default CHDR_W is 64 for RFNOC blocks when I want to create a custom RFNOC block, I know that the RFNOC bus block is AXI4, So for accessing samples I work with some registers in Verilog code ... m_in_payload_tdata Details I/Q samples are below... I/real in [63:32], Q/imaginary in [31:0] (sc32).

[USRP-users] What's the max legal value for these parameters in RFNOC blocks?

2022-03-14 Thread sp h
What's the max legal value for these parameters in RFNOC blocks? Can I for an RFNOC block set CHDR_W to 1024? We know for communication between RFNOC blocks in USRP is used AXI4 stream bus. thanks in advance parameter CHDR_W = 64, parameter [5:0] MTU = 10

[USRP-users] There is an example gain RFNOC block in an old document from UHD, but

2022-03-12 Thread sp h
There is an example gain RFNOC block in an old document from UHD but for the UHD 4 document this example (gain RFNOC block is removed...) For the new UHD document, NOC shell and pins are changed...anyone gain RFNOC block for UHD 4 and new documents? thanks very much Old doc: https://kb.ettus.c

[USRP-users] When I create a rfnoc block with rfnocmodtool, the block has default code...

2022-03-11 Thread sp h
When I create an RFNOC block with rfnocmodtool, the block has a default code... My question is what to do this default code for RFNOC block? It is a gain block? It is a buffer block? What is this code? can anyone guide me... // // Copyright 2022 <+YOU OR YOUR COMPANY+>. // // This is free

[USRP-users] Re: How can create an RFNOC correlate block for USRP?

2022-03-07 Thread sp h
); > >> z = xcorr(x,y); > >> Lfft = 2^nextpow2(2*L-1); > >> z2 = circshift(ifft(fft(x,Lfft).*conj(fft(y,Lfft)),Lfft),L-1); > >> plot(abs(z-z2(1:2*L-1))) > > On Fri, Feb 25, 2022 at 2:30 AM sp h wrote: > >> Thanks, I know that I can use FFT but I wa

[USRP-users] What's mean .debug () in RFNOC replay block?

2022-02-27 Thread sp h
I am reading RFNOC replay block, end of the Verilog code I faced a debug code ... what's mean debug? what does it do? axi_dma_master #( .AWIDTH (MEM_ADDR_W), .DWIDTH (MEM_DATA_W) ) axi_dma_master_i ( // // AXI4 Memory Mapped Interface to DRAM // .aclk (mem_clk), .areset (mem_rst), // Write contro

[USRP-users] Re: How can create an RFNOC correlate block for USRP?

2022-02-24 Thread sp h
Thanks, I know that I can use FFT but I want to implement Xcorrelate like xcorr Matlab directly...as an independent RFNOC blocks On Wed, Feb 23, 2022 at 10:56 AM sp h wrote: > Thanks, I know that I can use FFT but I want to implement Xcorrelate like > xcorr matlab directly...as a indep

[USRP-users] How can create an RFNOC correlate block for USRP?

2022-02-21 Thread sp h
How can create an RFNOC correlate block for USRP? This thread is created to share results on searching how we can correlate RFNOC blocks... Anyone that had an idea, I'm glad to hear it... thanks in advance ___ USRP-users mailing list -- usrp-users@lists.e

[USRP-users] Re: How to create the RFNOC block gain for other RFNOC image cores...Default is for X310, but I want to be x300?

2022-02-18 Thread sp h
Finally found the solution you should manually some files in the icores folder...For example for x300 go to this path in UHD/FPGA path:uhd-4.1.0.5/fpga/usrp3/top/x300 copy below files in icores folder.. and change name x300_rfnoc_image_core.yml to gain_x300_rfnoc_image_core.yml... for other ser

[USRP-users] Re: How to create the RFNOC block gain for other RFNOC image cores...Default is for X310, but I want to be x300?

2022-02-18 Thread sp h
Thanks, But for another model like B210 and is it not there anyway? On Fri, Feb 18, 2022 at 5:14 PM Cédric Hannotier wrote: > On 18/02/22 12:51, sp h wrote: > > On Sun, Feb 13, 2022 at 10:51 AM sp h wrote: > > > How to create the RFNOC block gain for other RFNOC image

[USRP-users] Re: How to create the RFNOC block gain for other RFNOC image cores...Default is for X310, but I want to be x300?

2022-02-18 Thread sp h
Does anyone have not any idea? thanks in advance On Sun, Feb 13, 2022 at 10:51 AM sp h wrote: > How to create the RFNOC block gain for other RFNOC image cores...Default > is for X310, but I want to be x300? > When I created a new RFNOC module with the below commands, the RFNNOC > i

[USRP-users] How to create the RFNOC block gain for other RFNOC image cores...Default is for X310, but I want to be x300?

2022-02-12 Thread sp h
How to create the RFNOC block gain for other RFNOC image cores...Default is for X310, but I want to be x300? When I created a new RFNOC module with the below commands, the RFNNOC image core is x310 (my Gnuradio 3.8.1, UHD 4.1.0.5). $rfnocmodtool newmod transceiver $cd rfnoc-transceiver $ rfnocmodto

[USRP-users] Re: Error in building USRP FPGA bitstream module 'rfnoc_block_fft' not found

2022-02-12 Thread sp h
Finally, I edited the RFNOC image core when I used the default RFNOC image core x300_rfnoc_image_core.yml, and run below command, I could successfully open UHD project in GUI vivado. Thanks very much make X300_HG GUI=1 On Thu, Feb 3, 2022 at 12:13 PM sp h wrote: > I reformed my previous p

[USRP-users] Re: Why RFNOC gain example building FPGA, I faced with module 'rfnoc_block_gain' not found?

2022-02-11 Thread sp h
the include path was wrong, so your Makefile.srcs wasn't > added. If you're coping the rfnoc-example, here's how to build it (I've > attempted to use your file paths in this example): > > cd /home/sp/Documents/rfnoc-tutorial > mkdir build > cd build > cmake

[USRP-users] Why RFNOC gain example building FPGA, I faced with module 'rfnoc_block_gain' not found?

2022-02-07 Thread sp h
I copied RFNOC gain example from UHD folder, I installed it successfully in Gnuradio, But for building FPGA I was faced with these errors. How can I solve this problem? Thanks in advance ERROR: [Synth 8-439] module 'rfnoc_block_gain' not found [/home/sp/Documents/rfnoc-tutorial/rf

[USRP-users] Re: Vivado: Version 2019.1 not found error when i want to a built a custom RFNOC block

2022-02-07 Thread sp h
Thank you for the clarification. When I used these commands: source setupenv.sh --vivado-path=/home/sp/xilinx/Vivado rfnoc_image_builder -F /home/sp/Documents/uhd-4.1.0.5/fpga -I /home/sp/Documents/rfnoc-tutorial/include/rfnoc -y /home/sp/Documents/rfnoc-tutorial/rfnoc/icores

[USRP-users] Re: Vivado: Version 2019.1 not found error when i want to a built a custom RFNOC block

2022-02-06 Thread sp h
Finally, I used the below command to built bitstream for FPGA... rfnoc_image_builder -F /home/sp/Documents/uhd-4.1.0.5/fpga -I /home/sp/Documents/rfnoc-example/include/rfnoc -y /home/sp/Documents/rfnoc-example/icores/x310_rfnoc_image_core.yml But I was faced with a strange error... RFNOC

[USRP-users] Re: Building FPGA [00:12:48] Process terminated. Status: Failure How much can I debug?

2022-02-06 Thread sp h
Yes, I commented on two other clock sections now I built the FPGA bitstream successfully... thanks very much > x300_with_fft (another copy).yml Description: application/yaml ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send

[USRP-users] Vivado: Version 2019.1 not found error when i want to a built a custom RFNOC block

2022-02-06 Thread sp h
I copied the RFNOC example in a folder. for building, I used these commands... Building and Installing an OOT Module mkdir build cd build cmake .. -DUHD_FPGA_DIR=/home/sp/Documents/uhd-4.1.0.5/fpga make Building an FPGA Image with OOT Blocks when I want to build FPGA I used these commands... make

[USRP-users] what's BSP connections in USRP RFNOC image core files?

2022-02-04 Thread sp h
Hi, In RFNOC image core files I saw that BSP connection? what's them and what's the difference between ordinary connections and BSP connections... thanks in advance *BSP connections:* # BSP Connections - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } - { sr

[USRP-users] Re: Building FPGA [00:12:48] Process terminated. Status: Failure How much can I debug?

2022-02-04 Thread sp h
cause. > > You could also share your x300_with_fft.yml contents so others can check > if they see anything wrong. > > Wade > > On Fri, Feb 4, 2022 at 11:12 AM sp h wrote: > >> No, I built FPGA from Ubuntu 20.04, a physical PC not VM. >> Ram is enough 12G, In other cases,

[USRP-users] Re: Building FPGA [00:12:48] Process terminated. Status: Failure How much can I debug?

2022-02-04 Thread sp h
build in a VM or on a system with a limited > amount of RAM? > > Jonathon > > On Fri, Feb 4, 2022 at 8:44 AM sp h wrote: > >> Finally, I found that... >> In Vivado there is a limit for the number of warnings and errors which >> are displayed by the tool f

[USRP-users] Re: Building FPGA [00:12:48] Process terminated. Status: Failure How much can I debug?

2022-02-04 Thread sp h
nces-of-the-messages-will-be-disabled-use-the-tcl-command-set_msg_config-to-change-the-current-settings/ https://support.xilinx.com/s/article/53034?language=en_US On Thu, Feb 3, 2022 at 1:29 PM sp h wrote: > When I want to build a new image configuration for USRP X300 I was faced >

[USRP-users] Building FPGA [00:12:48] Process terminated. Status: Failure How much can I debug?

2022-02-03 Thread sp h
When I want to build a new image configuration for USRP X300 I was faced with [00:12:48] Process terminated. Status: Failure my new RFNOC core image YAML file, I attached here... *And when I want to build I used these commands:* source setupenv.sh --vivado-path=/home/sp/xilinx/Vivado

[USRP-users] Re: Error in building USRP FPGA bitstream module 'rfnoc_block_fft' not found

2022-02-03 Thread sp h
I reformed my previous post, I used this command, so when I want to build with GUI=1 option I was faced with some errors make X300_HG GUI=1 but when I want to make without GUI=1 option I have not any eros... how can solve this problem? On Mon, Jan 31, 2022 at 2:40 PM sp h wrote: > when I w

[USRP-users] Error in building USRP FPGA bitstream module 'rfnoc_block_fft' not found

2022-01-31 Thread sp h
when I want to build an FPGA source for x300 (In Ubuntu 20.04, Gnuradio 3.8.1, uhd-4.1.0.5) I used the below command: source setupenv.sh --vivado-path=/home/sp/xilinx/Vivado make X300_HG But I have been faced with these errors... can any idea for solving this problem? [00:00:23] Starting

[USRP-users] When i want to add FFT block in FPGA image X300, I have errors 'NoneType' object has no attribute 'keys'

2022-01-28 Thread sp h
When I want to add an FFT block in FPGA image X300, I have errors 'NoneType' object has no attribute 'keys' I read the below link but I was faced with errors. https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0 I shared the file for x300_core.yml below... how can I fix the errors... Tra

[USRP-users] Re: For building Verilog code for FPGA x300 series which license Vivado should I necessary?

2022-01-16 Thread sp h
I'm sorry for the typo, I reformed it For building Verilog code (& generating bitstreams ) for the FPGA x300 series which Vivado license for a developer is necessary? Webpack license is enough? Or do we need a full license? thanks very much On Mon, Jan 17, 2022 at 10:47 AM sp h wrot

[USRP-users] For building Verilog code for FPGA x300 series which license Vivado should I necessary?

2022-01-16 Thread sp h
For building Verilog code for FPGA x300 series which license Vivado should I necessary? Webpack license is enough? Or do we need a full license? thanks very much ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to us

[USRP-users] UBX 160 transmit but only there is a small carrier....?

2022-01-13 Thread sp h
For USRP x310, I had UBX 160 daughterboard, but lately, however, RX works correctly But transmit mode is not working correctly. I had no data signal UBX 160 transmit but only there is a small carrier? For HackrfOne we had the same problem, we replace RF amplifier IC, now it works... b

[USRP-users] Which are RFNOC blocks used in UHD Sink/Source(UHD driver) in Gnuradio?

2022-01-08 Thread sp h
Which are RFNOC blocks used in UHD Sink/Source(UHD driver) in Gnuradio? I heard that the UHD sink or UHD source in Gnuradio is composed of some RFNOC blocks. When I see the RFNOC blocks, the Radio core is the same UHD but does anyone know which RFNOC blocks list are used in the UHD driver? thanks

[USRP-users] why my emails is not found on your forum? my emails is not delivered to usrp-user mailing list?

2022-01-07 Thread sp h
thanks, Marcus D. Leech, Anyway I sent thanks email with the subject root message. ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com

[USRP-users] How I can create a correlate RFNOC block, I need a where that buffer radio samples...

2022-01-07 Thread sp h
How I can create a correlate RFNOC block, I need a where that buffer radio samples... For more information (time-domain) correlate formula please refer to the below link: https://en.wikipedia.org/wiki/Cross-correlation I have a reference signal that should be correlated with the input signal recei

[USRP-users] why my emails is not found on your forum? my emails is not delivered to usrp-user mailing list?

2022-01-07 Thread sp h
Hi, for sending my questions, with Gmail I send an email to this address usrp-users@lists.ettus.com... The first email is delivered and everything is ok, but the replay email for me was not delivered... can anyone help me? why the second and third messages are not delivered? thanks in advance _

[USRP-users] Can any guide me in rfnoc blocks?

2022-01-03 Thread sp h
Hi, I am studying RFNOC blocks for USRP, the file that I am reading is in the below link... https://files.ettus.com/app_notes/RFNoC_Specification.pdf I know Verilog language, so another part I am studying RFNOC blocks Verilog Code. However knowing Verilog and RFNoC_Specification is not enough, be

[USRP-users] what's means uhd::multi_usrp API? it is not for me clear

2021-12-27 Thread sp h
I am studying RFNOC specifications. https://files.ettus.com/app_notes/RFNoC_Specification.pdf in the RFNOC software framework, it describes uhd::multi_usrp API. but it is not clear to me? my question is which is the work of this API? can anyone explain more about it? uhd::multi_usrp API An RFNoC

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