Finally, I used the below command to built bitstream for FPGA... rfnoc_image_builder -F /home/sp/Documents/uhd-4.1.0.5/fpga -I /home/sp/Documents/rfnoc-example/include/rfnoc -y /home/sp/Documents/rfnoc-example/icores/x310_rfnoc_image_core.yml But I was faced with a strange error... RFNOC example for gain that there is in UHD file has errors...
[ERR] 1 unresolved clk domain(s) [ERR] gain0:ce [ERR] Please specify the clock(s) to connect On Sun, Feb 6, 2022 at 7:38 PM sp h <stackprogra...@gmail.com> wrote: > I copied the RFNOC example in a folder. for building, I used these > commands... > Building and Installing an OOT Module > mkdir build > cd build > cmake .. -DUHD_FPGA_DIR=/home/sp/Documents/uhd-4.1.0.5/fpga > make > Building an FPGA Image with OOT Blocks > when I want to build FPGA I used these commands... > > make x310_rfnoc_image_core > > I faced with this error > *Errors:* > > > > *Setting up a 64-bit FPGA build environment for the USRP-X3x0...- Vivado: > Version 2019.1 not found in /opt/Xilinx/Vivado (ERROR.. Builds and > simulations will not work) Use the --vivado-path option to > override the search pathBuilt target x310_rfnoc_image_core* > > When I used these options I was faced another error... > > make x310_rfnoc_image_core --vivado-path=/home/sp/xilinx/Vivado > > *Errors:* > make: unrecognized option '--vivado-path=/home/sp/xilinx/Vivado' > > How can build Gain RFNOC example successfully? > thanks in advance > > > > > >
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