Hi, I am studying RFNOC blocks for USRP, the file that I am reading is in the below link... https://files.ettus.com/app_notes/RFNoC_Specification.pdf I know Verilog language, so another part I am studying RFNOC blocks Verilog Code.
However knowing Verilog and RFNoC_Specification is not enough, because I think I am faced with a Verilog framework for kintex7. So I had some questions yet. Verilog code for an RFNOC block has two main files for example: for gain example, we have two files: noc_shell_gain.v rfnoc_block_gain.v my question is about noc_shell_gain.v file. there is a section defining the input module... anyone can guide me on whats do this section(Client Interface)? what's the difference between this section and the Framework Interface section? what's the difference between context and payload streams? thanks in advance //--------------------- // Framework Interface //--------------------- // RFNoC Framework Clocks input wire rfnoc_chdr_clk, input wire rfnoc_ctrl_clk, // NoC Shell Generated Resets output wire rfnoc_chdr_rst, output wire rfnoc_ctrl_rst, // RFNoC Backend Interface input wire [511:0] rfnoc_core_config, output wire [511:0] rfnoc_core_status, // AXIS-CHDR Input Ports (from framework) input wire [(1)*CHDR_W-1:0] s_rfnoc_chdr_tdata, input wire [(1)-1:0] s_rfnoc_chdr_tlast, input wire [(1)-1:0] s_rfnoc_chdr_tvalid, output wire [(1)-1:0] s_rfnoc_chdr_tready, // AXIS-CHDR Output Ports (to framework) output wire [(1)*CHDR_W-1:0] m_rfnoc_chdr_tdata, output wire [(1)-1:0] m_rfnoc_chdr_tlast, output wire [(1)-1:0] m_rfnoc_chdr_tvalid, input wire [(1)-1:0] m_rfnoc_chdr_tready, // AXIS-Ctrl Control Input Port (from framework) input wire [31:0] s_rfnoc_ctrl_tdata, input wire s_rfnoc_ctrl_tlast, input wire s_rfnoc_ctrl_tvalid, output wire s_rfnoc_ctrl_tready, // AXIS-Ctrl Control Output Port (to framework) output wire [31:0] m_rfnoc_ctrl_tdata, output wire m_rfnoc_ctrl_tlast, output wire m_rfnoc_ctrl_tvalid, input wire m_rfnoc_ctrl_tready, //--------------------- // Client Interface //--------------------- // CtrlPort Clock and Reset output wire ctrlport_clk, output wire ctrlport_rst, // CtrlPort Master output wire m_ctrlport_req_wr, output wire m_ctrlport_req_rd, output wire [19:0] m_ctrlport_req_addr, output wire [31:0] m_ctrlport_req_data, input wire m_ctrlport_resp_ack, input wire [31:0] m_ctrlport_resp_data, // AXI-Stream Payload Context Clock and Reset output wire axis_data_clk, output wire axis_data_rst, // Payload Stream to User Logic: in output wire [32*1-1:0] m_in_payload_tdata, output wire [1-1:0] m_in_payload_tkeep, output wire m_in_payload_tlast, output wire m_in_payload_tvalid, input wire m_in_payload_tready, // Context Stream to User Logic: in output wire [CHDR_W-1:0] m_in_context_tdata, output wire [3:0] m_in_context_tuser, output wire m_in_context_tlast, output wire m_in_context_tvalid, input wire m_in_context_tready, // Payload Stream from User Logic: out input wire [32*1-1:0] s_out_payload_tdata, input wire [0:0] s_out_payload_tkeep, input wire s_out_payload_tlast, input wire s_out_payload_tvalid, output wire s_out_payload_tready, // Context Stream from User Logic: out input wire [CHDR_W-1:0] s_out_context_tdata, input wire [3:0] s_out_context_tuser, input wire s_out_context_tlast, input wire s_out_context_tvalid, output wire s_out_context_tready
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