Thanks very much, Marcus. Can explain more? I had not any idea how develop your way?
On Mon, Nov 7, 2022 at 11:29 PM Marcus Müller <marcus.muel...@ettus.com> wrote: > Hi sp, > > That sounds like a bad idea. How are you planning to synchronize access to > that register? > > Generally, in almost *any* context, avoid global state. That makes things > complicated and > error prone; this is true for python as much as it is for C++, as much as > it is for > digital hardware design (in verilog or any other way); it's even true for > design of > mechanical machine factory floors (if you make each processing step as > independent from > the other as possible, you increase reliability). > > So, I'd recommend you find a different way to exchange information between > two blocks. > Exchanging information is the point of RFNoC, by the way. > > Best regards, > Marcus > > On 31.07.22 17:52, sp wrote: > > How can I define a global reg variable in Verilog between RFNOC blocks? > > I developed two RFNOC blocks: RFNOC block A, and RFNOC block B > > How can define a reg variable that shares between RFNOC blocks in USRP? > > Can anyone guide me? > > > > I study about global reg variable in the Verilog module, see below > link, but I can not > > do it for RFNOC blocks... > > How can implement this mechanism in RFNOC blocks > > > https://www.edaboard.com/threads/how-to-define-global-variable-in-verilog.174172/ > > > > Thanks in advance > > > > _______________________________________________ > > USRP-users mailing list -- usrp-users@lists.ettus.com > > To unsubscribe send an email to usrp-users-le...@lists.ettus.com > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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