How can I define a global reg variable in Verilog between RFNOC blocks? I developed two RFNOC blocks: RFNOC block A, and RFNOC block B How can define a reg variable that shares between RFNOC blocks in USRP? Can anyone guide me?
I study about global reg variable in the Verilog module, see below link, but I can not do it for RFNOC blocks... How can implement this mechanism in RFNOC blocks https://www.edaboard.com/threads/how-to-define-global-variable-in-verilog.174172/ Thanks in advance
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