Hi, I tested your way but I have challenges with it. I described it in
the below link. do you have any offer?
Thanks very much

https://lists.ettus.com/empathy/thread/A65LFSBUISOLPBGIRJWSJYBESRPMPEPC

On Mon, Aug 1, 2022 at 1:47 PM Paolo Palana <p.pal...@itsystems.it> wrote:

> For experimental purpose I did something like you say.
>
> Referring to usrp X300
>
> 1. add the reg variable to rfnoc_ce_default_inst_x300.v (or the relevant
> file for your radio)
>
> 2. add to the noc _block module declaration an additional input port e.g.
>
> module noc_test #(
>    parameter NOC_ID = 64'h1234_0000_0000_1234,
>    parameter STR_SINK_FIFOSIZE = 11,
>    parameter NUM_PORTS  = 1)
> (
>    input bus_clk, input bus_rst,
>    input ce_clk, input ce_rst,
>    input  [63:0] my_new_port,            <---- EXAMPLE, this is my new port
>    input  [63:0] i_tdata, input  i_tlast, input  i_tvalid, output i_tready,
>    output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
>    output [63:0] debug
> );
>
>
> 3. inside rfnoc_ce_default_inst_x300.v (or the relevant file for your
> radio) connect the reg variable with the
>
> new port on the noc_block
>
> 4. Now you can manage the (shared) reg variable from inside the noc block.
>
> Hope this can be of some help.
>
> Have a good day,
>
> paolo
>
> On 7/31/22 17:52, sp wrote:
> > How can I define a global reg variable in Verilog between RFNOC blocks?
> > I developed two RFNOC blocks: RFNOC block A, and RFNOC block B
> > How can define a reg variable that shares between RFNOC blocks in USRP?
> > Can anyone guide me?
> >
> > I study about global reg variable in the Verilog module, see below
> > link,  but I can not do it for RFNOC blocks...
> > How can implement this mechanism in RFNOC blocks
> >
> https://www.edaboard.com/threads/how-to-define-global-variable-in-verilog.174172/
> >
> > Thanks in advance
> >
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