I want to use sine ton verilog file in my rfnoc block file, How Can add sine tone file and ... to my rfnoc block how can solve my problems? my Verilog file are in this path uhd-4.1.0.5/fpga/usrp3/lib/rfnoc Thanks in advance
RROR: [VRFC 10-2063] Module <sine_tone> not found while processing module instance <sine_tone_i> [/home/sp/rfnoc-test/rfnoc/fpga/rfnoc_block_gain/correlate.v:132] ERROR: [VRFC 10-2063] Module <rng> not found while processing module instance <rng_i> [/home/sp/rfnoc-test/rfnoc/fpga/rfnoc_block_gain/correlate.v:164] #------------------------------------------------- # Top-of-Makefile #------------------------------------------------- # Define BASE_DIR to point to the "top" dir. Note: # UHD_FPGA_DIR must be passed into this Makefile. ifndef UHD_FPGA_DIR $(error "UHD_FPGA_DIR is not set! Must point to UHD FPGA repository!") endif BASE_DIR = $(UHD_FPGA_DIR)/usrp3/top # Include viv_sim_preample after defining BASE_DIR include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak #------------------------------------------------- # Design Specific #------------------------------------------------- # Include makefiles and sources for the DUT and its # dependencies. include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs include Makefile.srcs DESIGN_SRCS += $(abspath $(RFNOC_CORE_SRCS) $(RFNOC_UTIL_SRCS) $(RFNOC_OOT_SRCS) ) #------------------------------------------------- # Testbench Specific #------------------------------------------------- SIM_TOP = rfnoc_block_gain_tb SIM_SRCS = $(abspath rfnoc_block_gain_tb.sv) #------------------------------------------------- # Bottom-of-Makefile #------------------------------------------------- # Include all simulator specific makefiles here # Each should define a unique target to simulate # e.g. xsim, vsim, etc and a common "clean" target include $(BASE_DIR)/../tools/make/viv_simulator.mak
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