Thanks for the feedback! But to save time I need to launch a simulation for my custom block, building fpga takes long time, Can anyone guide me fix my problem in custom rfnoc block?
On Wed, Aug 23, 2023 at 8:25 PM Wade Fife <wade.f...@ettus.com> wrote: > A testbench timeout is intended to prevent the test from waiting forever > for something that's not working. So if it's timing out, it's either > because the timeout is too short or because the thing it's waiting for is > not happening. Try searching for the timeout message text to see where the > timeout is created and why. You can of course remove the timeout, but that > won't necessarily fix the problem. > > Wade > > On Tue, Aug 22, 2023 at 12:55 AM sp <stackprogra...@gmail.com> wrote: > >> I write a custom block when i run test bench on it i faced with strange >> error,How can solve it i shared the custom rfnoc blocks >> Thanks in advance >> >> TESTBENCH STARTED: rfnoc_block_gain_tb >> ======================================================== >> [TEST CASE 1] (t = 0 ns) BEGIN: Flush block then reset it... >> [TEST CASE 1] (t = 6400 ns) DONE... Passed >> [TEST CASE 2] (t = 6400 ns) BEGIN: Verify Block Info... >> [TEST CASE 2] (t = 6400 ns) DONE... Passed >> [TEST CASE 3] (t = 6400 ns) BEGIN: Verify user register... >> [TEST CASE 3] (t = 7725 ns) DONE... Passed >> [TEST CASE 4] (t = 7725 ns) BEGIN: Test passing through samples... >> Fatal: Timeout: Test "Test passing through samples" time limit exceeded >> Time: 17725 ns Iteration: 0 Process: >> /PkgTestExec/TestExec::start_timeout/Block260_9/timeout File: >> /home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/sim/rfnoc/PkgTestExec.sv >> _______________________________________________ >> USRP-users mailing list -- usrp-users@lists.ettus.com >> To unsubscribe send an email to usrp-users-le...@lists.ettus.com >> >
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