Thank you for the clarification. When I used these commands:
source setupenv.sh --vivado-path=/home/sp/xilinx/Vivado
rfnoc_image_builder -F /home/sp/Documents/uhd-4.1.0.5/fpga -I
/home/sp/Documents/rfnoc-tutorial/include/rfnoc -y
/home/sp/Documents/rfnoc-tutorial/rfnoc/icores/gain_x310_rfnoc_image_core.yml
--vivado-path=/home/sp/xilinx/Vivado
But after it, I was faced with these errors? This is an RFNOC example for
gain block why It doesn't work correctly
ERROR: [Synth 8-439] module 'rfnoc_block_gain' not found
[/home/sp/Documents/rfnoc-tutorial/rfnoc/icores/x310_rfnoc_image_core.v:1055]
ERROR: [Synth 8-6156] failed synthesizing module 'rfnoc_image_core'
[/home/sp/Documents/rfnoc-tutorial/rfnoc/icores/x310_rfnoc_image_core.v:24]
ERROR: [Synth 8-6156] failed synthesizing module 'bus_int'
[/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/bus_int.v:9]
ERROR: [Synth 8-6156] failed synthesizing module 'x300_core'
[/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/x300_core.v:9]
ERROR: [Synth 8-6156] failed synthesizing module 'x300'
[/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/x300.v:20]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the
console or run log file for details
[00:04:31] Current task: Synthesis +++ Current Phase: Starting
[00:04:31] Current task: Synthesis +++ Current Phase: Finished
[00:04:31] Process terminated. Status: Failure
On Mon, Feb 7, 2022 at 7:15 PM Wade Fife <wade.f...@ettus.com> wrote:
> Hi sp,
>
> Regarding the error message about Vivado not being found. You need to set
> up your environment before building an FPGA. rfnoc_image_builder does this
> automatically for you. But if you run make directly then you need to source
> setupenv.sh manually. For example:
>
> source uhd/fpga/usrp3/top/x300/setupenv.sh
>
> The error about the unresolved clock domain means you need to connect a
> clock to the ce clock input of your gain block. The tools expects something
> like this in your YAML file:
>
> clk_domains:
> - { srcblk: _device_, srcport: ce, dstblk: gain0, dstport: ce }
>
> However, the gain example in UHD doesn't have a ce clock port, so I assume
> you modified the example to add that clock port. The tool requires all
> clock inputs to be connected.
>
> Wade
>
>
> On Mon, Feb 7, 2022 at 5:56 AM Arash Jafari <
> arash.jafari.tele...@gmail.com> wrote:
>
>> Hello sp h,
>>
>> I did it about 3 years ago, as I remember, there is a Tcl file in the
>> make folder or s.w else the Vivado version is defined there, you need to
>> change the Vivado version there.
>> Please keep this in mind, in some scenarios the Vivado version must be
>> exactly the same as configured in the mentioned Tcl file, otherwise due to
>> some kind of incompatibility you can't proceed.
>> use *grep -r vivado *command or s.t similar in ubuntu to find where to
>> configure it.
>>
>> Kind Regards
>> ------------------------
>> Dipl.-Ing. Arash Jafari
>> Phone: +43 650 844 3617
>> E-mail: arash.jafari.tele...@gmail.com
>>
>> On Sun, Feb 6, 2022 at 5:10 PM sp h <stackprogra...@gmail.com> wrote:
>>
>>> I copied the RFNOC example in a folder. for building, I used these
>>> commands...
>>> Building and Installing an OOT Module
>>> mkdir build
>>> cd build
>>> cmake .. -DUHD_FPGA_DIR=/home/sp/Documents/uhd-4.1.0.5/fpga
>>> make
>>> Building an FPGA Image with OOT Blocks
>>> when I want to build FPGA I used these commands...
>>>
>>> make x310_rfnoc_image_core
>>>
>>> I faced with this error
>>> *Errors:*
>>>
>>>
>>>
>>> *Setting up a 64-bit FPGA build environment for the USRP-X3x0...-
>>> Vivado: Version 2019.1 not found in /opt/Xilinx/Vivado (ERROR.. Builds and
>>> simulations will not work) Use the --vivado-path option to
>>> override the search pathBuilt target x310_rfnoc_image_core*
>>>
>>> When I used these options I was faced another error...
>>>
>>> make x310_rfnoc_image_core --vivado-path=/home/sp/xilinx/Vivado
>>>
>>> *Errors:*
>>> make: unrecognized option '--vivado-path=/home/sp/xilinx/Vivado'
>>>
>>> How can build Gain RFNOC example successfully?
>>> thanks in advance
>>>
>>>
>>>
>>>
>>>
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>>>
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