Thanks for the tip! But for usual cases it works.....$readmemhex works like
charm....when I use a for or loop and I used ROM in for I faced with these
errors.....see the source code an RFNOC block code
module multiplier_core
#(parameter WIDTH=64)
(input clk, input reset,input [31:0] reg_user,
input [32-1:0] config_tdata, input config_tlast, input config_tvalid, output
config_tready,
output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
reg signed [15:0] data_samples_i_buffer [1024:0];
reg signed [15:0] data_samples_q_buffer [1024:0];
reg [31:0] edgei_tbl_rom[0:1024];
reg [31:0] edgeq_tbl_rom[0:1024];
initial begin
//Initial
$readmemh("/home/sp/rfnoc-test/rfnoc/fpga/rfnoc_block_multiplier/1.hex"
,edgei_tbl_rom,0,1024);
$readmemh("/home/sp/rfnoc-test/rfnoc/fpga/rfnoc_block_multiplier/1.hex"
,edgeq_tbl_rom,0,1024);
ebd
always @(posedge config_tvalid ) begin
if(state==1)
begin
$display("-------Clock is triggerted...%0d ----",m);
//Save samples in samples buffer
data_samples_i_buffer[m]=config_tdata[15:0];
data_samples_q_buffer[m]=config_tdata[31:16];
$display("Sample %0d = %0d +i %0d"
,m,data_samples_i_buffer[m],data_samples_q_buffer[m]);
if(m==1024) begin
m=0;
end else begin
m=m+1;
end
// temp_i_mult_result_sum= edge_tbl_rom[j];
for(j=0; j<1000; j=j+1)
begin
temp_i_mult_result_sum= edgei_tbl_rom[j];
//(temp_i_mult_result_sum+data_samples_i_buffer[j]*edgei_tbl_rom[j]+data_samples_q_buffer[j]*edgeq_tbl_rom[j]);
end
// energy_factor=reg_user;//65536*20;
multiplier_tdata=temp_i_mult_result_sum;
temp_i_mult_result_sum=0;
end
else begin
end
end
assign o_tdata = { 32'h00000000, multiplier_tdata};
assign o_tlast = config_tlast;
assign o_tvalid = config_tvalid;
assign config_tready = o_tready;
endmodule
On Fri, Oct 21, 2022 at 9:19 PM Wade Fife <wade.f...@ettus.com> wrote:
> I'm curious if it works if you change the memory size to 1024 instead of
> 1025 like you have now, or if you use increasing addresses instead of
> decreasing. A 1025-word memory with a reversed range is unusual. But
> regardless, this warning comes from Vivado, not UHD/RFNoC, so you should
> probably post your question on the Vivado forum.
>
> Wade
>
> On Sat, Oct 15, 2022 at 10:03 AM sp <stackprogra...@gmail.com> wrote:
>
>> Yes, it is. I attached some example file. I changed name of them in code
>> but I am faced with a warning.........
>> WARNING: [Synth 8-2898] ignoring malformed $readmem task: invalid memory
>> name [file.sv:50]
>> WARNING: [Synth 8-2898] ignoring malformed $readmem task: invalid memory
>> name [file.sv:51]
>> In simulation it works but i synthesis I am faced with top
>> warning..........
>> why in RFNOC block I faced with this error for mem files.........can any
>> one guide me?
>>
>> On Fri, Oct 14, 2022 at 7:36 PM Wade Fife <wade.f...@ettus.com> wrote:
>>
>>> Does the file you're reading from have enough data in it?
>>>
>>> Wade
>>>
>>>
>>> On Thu, Oct 13, 2022, 7:39 AM sp <stackprogra...@gmail.com> wrote:
>>>
>>>> Why initialize large array in Verilog is not successfully. When size of
>>>> array is 255 it work like charm but for other number more than 255 like
>>>> 1024 and ....
>>>> we observe all array is filled with zero? why large array in FPGA can
>>>> not initailize correctly????
>>>>
>>>>
>>>> Code:
>>>> reg signed [15:0] data_i_pattern_buffer [1024:0];
>>>> reg signed [15:0] data_q_pattern_buffer [1024:0];
>>>> $readmemh("out_i.txt",data_i_pattern_buffer,0,1024);
>>>> $readmemh("out_q.txt",data_q_pattern_buffer,0,1024);
>>>> _______________________________________________
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>>>>
>>>
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