Hi, when I changed the name of the Gain block to another name, I want to
run the test bench and simulated it but I was faced with these errors.......
How can solve my problems?
========================================================
TESTBENCH STARTED: chdr_crossbar_nxn: IP_OPTION = HDL_IP
========================================================
[TEST CASE 1] (t = 0 ns) BEGIN: Flush block then reset it...
[TEST CASE 1] (t = 6450 ns) DONE... Passed
[TEST CASE 2] (t = 6450 ns) BEGIN: Verify Block Info...
Error: Incorrect NOC_ID Value
Time: 6450 ns Iteration: 1 Process:
/rfnoc_block_correlate_tb/Initial172_431 File:
/home/sp/Documents/rfnoc-transceiver/rfnoc/fpga/rfnoc_block_correlate/
rfnoc_block_correlate_tb.sv
$stop called at time : 6450 ns : File
"/home/sp/Documents/rfnoc-transceiver/rfnoc/fpga/rfnoc_block_correlate/
rfnoc_block_correlate_tb.sv" Line 201
INFO: [USF-XSim-96] XSim completed. Design snapshot
'rfnoc_block_correlate_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000000000us
launch_simulation: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory
(MB): peak = 1484.270 ; gain = 64.477 ; free physical = 294 ; free virtual
= 9811
# if { [info exists ::env(VIV_SYNTH_TOP)] } {
# puts "BUILDER: Synthesizing"
# # Synthesize requested modules
# foreach synth_top "$::env(VIV_SYNTH_TOP)" {
# set_property top $synth_top [current_fileset]
# synth_design -mode out_of_context
# # Perform a simple regex-based search for all clock signals and
constrain
# # them to 500 MHz for the timing report.
# set clk_regexp "(?i)^(?!.*en.*).*(clk|clock).*"
# foreach clk_inst [get_ports -regexp $clk_regexp] {
# create_clock -name $clk_inst -period 2.0 [get_ports $clk_inst]
# }
# report_utilization -no_primitives -file
${working_dir}/${synth_top}_synth.rpt
# report_timing_summary -setup -max_paths 3 -unique_pins -no_header
-append -file ${working_dir}/${synth_top}_synth.rpt
# write_checkpoint -force ${working_dir}/${synth_top}_synth.dcp
# }
# } else {
# puts "BUILDER: Skipping resource report because VIV_SYNTH_TOP is not
set"
# }
BUILDER: Synthesizing
# if [string equal $vivado_mode "batch"] {
# puts "BUILDER: Closing project"
# close_project
# } else {
# puts "BUILDER: In GUI mode. Leaving project open."
# }
BUILDER: Closing project
INFO: [Common 17-206] Exiting Vivado at Sun Apr 17 09:55:45 2022...
Built target rfnoc_block_correlate_tb
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