When I want to build the rfnoc-example that is in the UHD-4.1.05 folder I
am faced with the ce_clock error...
In this example, there is an Incompatibility clock domain.In file gain.yml
we see that there not any ce_clock domain...
//gain.yml section
clocks:
- name: rfnoc_chdr
freq: "[]"
- name: rfnoc_ctrl
freq: "[]"
But in file x310_rfnoc_image_core.yml we have not defined any clock for
gain blocks.
Why this RFNOC example not build successfully? Anyone has a idea? when I
added ce clock domain in file image core and defined
a wire ce_clk, Even bitstream is generated but block not work correctly in
Gnuradio and we have bad packet errors...
//x310_rfnoc_image_core.yml
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
Error ce_clk:
[00:00:22] Starting Synthesis Command
ERROR: [Synth 8-448] named port connection 'ce_clk' does not exist for
instance 'b_gain0_6' of module 'rfnoc_block_gain'
[/home/sp/Documents/rfnoc-transceiver/rfnoc/icores/x300_rfnoc_image_core.v:1058]
ERROR: [Synth 8-6156] failed synthesizing module 'rfnoc_image_core'
[/home/sp/Documents/rfnoc-transceiver/rfnoc/icores/x300_rfnoc_image_core.v:24]
ERROR: [Synth 8-6156] failed synthesizing module 'bus_int'
[/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/bus_int.v:9]
ERROR: [Synth 8-6156] failed synthesizing module 'x300_core'
[/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/x300_core.v:9]
ERROR: [Synth 8-6156] failed synthesizing module 'x300'
[/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/x300.v:20]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the
console or run log file for details
[00:03:42] Current task: Synthesis +++ Current Phase: Starting
[00:03:43] Current task: Synthesis +++ Current Phase: Finished
[00:03:43] Process terminated. Status: Failure
========================================================
Warnings: 315
Critical Warnings: 1
Errors: 6
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