Thanks for the feedback! I will test them. On Tue, Jun 14, 2022 at 1:42 AM Wade Fife <wade.f...@ettus.com> wrote:
> Hi sp, > > It is possible to use incremental implementation using the checkpoints > generated by the build flow, but I've never tried it with USRPs. This is an > advanced Vivado feature so you would need to write your own TCL code to use > that feature. See the Xilinx documentation for details. Keep in mind that > this is only for implementation (not for synthesis) and it's only > recommended for small and isolated design changes. > > Also, make sure when you run the build process that it's not regenerating > the IP. IP generation/synthesis should only happen once then those results > should be reused for each future build. But if you do "make cleanall" it > will delete all the IP build results. > > A good way to reduce compilation time is to remove the parts of the RFNoC > Image Core that you don't need. For example, if you are only doing RX then > you can remove the TX paths, including the DUCs. If you're not using all > the radio ports, you can remove the radio blocks and paths that you aren't > using. And if you're not using the replay block then you should definitely > remove that since that takes a long time to build. > > Also, you should not be rebuilding frequently, ideally. Simulation is a > much faster way to debug and test changes to your code. So it's usually > worth spending some time building a good testbench to make sure everything > works the way you expect before you rebuild the FPGA. > > Wade > > > On Sun, Jun 12, 2022 at 2:40 AM sp h <stackprogra...@gmail.com> wrote: > >> Is it possible that synthesis and generating bitstream in RFNOC blocks >> make faster??!!! >> I developed a custom RFNOC block, (I used example gain for RFNOC block) >> but when I want to synthesize Verilog code It takes long about 2 hours... >> For building the RFNOC bitstream image I used the below command: >> >> >>> rfnoc_image_builder -F /home/sp/Documents/uhd-4.1.0.5/fpga -I >>> /home/sp/Documents/rfnoc-module -p /home/sp/xilinx/Vivado -y >>> /home/sp/Documents/rfnoc-module/rfnoc/icores/gain_x300_rfnoc_image_core.yml >> >> >> My question is there any option that makes RFNOC synthesis faster? like >> incremental-implementation-vivado or any same case. >> >> https://www.xilinx.com/video/hardware/incremental-implementation-vivado.html >> >> Thanks in advance >> _______________________________________________ >> USRP-users mailing list -- usrp-users@lists.ettus.com >> To unsubscribe send an email to usrp-users-le...@lists.ettus.com >> >
_______________________________________________ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
