When I run the gain example testbench file I am faced with errors.....How
can I solve this?
Vivado Simulator does not support tracing of System Verilog Dynamic Type
object.
========================================================
TESTBENCH STARTED: rfnoc_block_gain_tb
========================================================
[TEST CASE 1] (t = 0 ns) BEGIN: Flush block then reset it...
*Fatal: Timeout: Test "Flush block then reset it" time limit exceeded*Time:
10 us Iteration: 0 Process:
/PkgTestExec/TestExec::start_timeout/Block260_9/timeout File:
/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/sim/rfnoc/PkgTestExec.sv
$finish called at time : 10 us : File
"/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/sim/rfnoc/PkgTestExec.sv" Line
235
INFO: [USF-XSim-96] XSim completed. Design snapshot
'rfnoc_block_gain_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000000000us
launch_simulation: Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory
(MB): peak = 1462.531 ; gain = 80.324 ; free physical = 285 ; free virtual
= 9898
# if { [info exists ::env(VIV_SYNTH_TOP)] } {
# puts "BUILDER: Synthesizing"
# # Synthesize requested modules
# foreach synth_top "$::env(VIV_SYNTH_TOP)" {
# set_property top $synth_top [current_fileset]
# synth_design -mode out_of_context
# # Perform a simple regex-based search for all clock signals and
constrain
# # them to 500 MHz for the timing report.
# set clk_regexp "(?i)^(?!.*en.*).*(clk|clock).*"
# foreach clk_inst [get_ports -regexp $clk_regexp] {
# create_clock -name $clk_inst -period 2.0 [get_ports $clk_inst]
# }
# report_utilization -no_primitives -file
${working_dir}/${synth_top}_synth.rpt
# report_timing_summary -setup -max_paths 3 -unique_pins -no_header
-append -file ${working_dir}/${synth_top}_synth.rpt
# write_checkpoint -force ${working_dir}/${synth_top}_synth.dcp
# }
# } else {
# puts "BUILDER: Skipping resource report because VIV_SYNTH_TOP is not
set"
# }
BUILDER: Synthesizing
# if [string equal $vivado_mode "batch"] {
# puts "BUILDER: Closing project"
# close_project
# } else {
# puts "BUILDER: In GUI mode. Leaving project open."
# }
BUILDER: Closing project
INFO: [Common 17-206] Exiting Vivado at Thu Feb 10 10:02:45 2022...
make[4]: warning: Clock skew detected. Your build may be incomplete.
make[3]: warning: Clock skew detected. Your build may be incomplete.
Built target rfnoc_block_gain_tb
make[2]: warning: Clock skew detected. Your build may be incomplete.
make[1]: warning: Clock skew detected. Your build may be incomplete.
make: warning: Clock skew detected. Your build may be incomplete.
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