On Thu, 9 Aug 2012, Phil Staub wrote:
> > > > > For this purpose the usual approach is to follow up to the patch
> > > > > mail saying "Ping" and giving a url to the patch in patchwork,
> > > > > like this one:
> > > > > http://patchwork.ozlabs.org/patch/163705/
> > > > >
> > > > > Eventually som
Andreas,
> >> Actually there were better patches for the same bug by Meador, including
> >> git-style rather than SVN patches and adding a helper to initialize it
> >> consistently at all call sites.
I find quilt patches easier to manage when I need to reorder them,
revert, manually edit the di
Hi Andreas,
> > I find quilt patches easier to manage when I need to reorder them,
> > revert, manually edit the diffs (that I routinely do), etc. Perhaps I'm
> > just outdated, but that's the workflow I've found most efficient for me
> > while not disturbing anyone else. I've used quilt pat
On Tue, 4 Sep 2012, Jan Kiszka wrote:
> What I'm trying to understand and translate from the description is
> rather "note that for inputs a high-to-low transition cancels the
> interrupt as in the level-triggered mode." This is surely not what we do
> right now. OTOH, I'm afraid that switching to
On Mon, 3 Sep 2012, Jan Kiszka wrote:
> > - Qemu output (without this patch):
> > elcr=0c00 cmdRead ummask mask sti irq15 unmask DONE
> >
> > But on real hardware, the master seems to treat IRQ2 as level triggered,
That is not universally true, however in reality it does not matter, m
On Tue, 4 Sep 2012, Jan Kiszka wrote:
> >> What I'm trying to understand and translate from the description is
> >> rather "note that for inputs a high-to-low transition cancels the
> >> interrupt as in the level-triggered mode." This is surely not what we do
> >> right now. OTOH, I'm afraid that
On Mon, 10 Sep 2012, Avi Kivity wrote:
> >>> So the only difference between edge triggered and level triggered
> >>> is in the leading edge, with no difference in the trailing edge.
> >>
> >> Hard to believe. So an edge while cpu interrupts are disabled is ignored?
Please note that x86 CPU's I
On Sun, 9 Sep 2012, Matthew Ogilvie wrote:
> This bug manifested itself when the guest was Microport UNIX
> System V/386 v2.1 (ca. 1987), because it would sometimes mask
> off IRQ14 in the slave IMR after it had already been asserted.
> The master would still try to deliver an interrupt even thoug
On Mon, 10 Sep 2012, Matthew Ogilvie wrote:
> > > This bug manifested itself when the guest was Microport UNIX
> > > System V/386 v2.1 (ca. 1987), because it would sometimes mask
> > > off IRQ14 in the slave IMR after it had already been asserted.
> > > The master would still try to deliver an int
On Wed, 12 Sep 2012, Matthew Ogilvie wrote:
> Also, how big of a concern is a very rare gained or lost IRQ0
> actually? Under normal conditions, I would expect this to at most
> cause a one time clock drift in the guest OS of a fraction of
> a second. If that only happens when rebooting or migra
On Thu, 13 Sep 2012, Jan Kiszka wrote:
> > I've also just skimmed parts of the 8254 section of "The Indispensable PC
> > Hardware Book", by Hans-Peter Messmer, Copyright 1994 Addison-Wesley,
> > although I probably ought to read it more carefully.
>
> http://download.intel.com/design/archives/per
On Fri, 1 Aug 2014, Yongbok Kim wrote:
> Ping!
> Patch for v2.1.0
>
> -Original Message-
> From: Yongbok Kim
> Sent: 01 July 2014 17:43
> To: qemu-devel@nongnu.org
> Cc: aurel...@aurel32.net; Leon Alrae; Cristian Cuna; Yongbok Kim
> Subject: [PATCH v2] target-mips: fix broken MIPS16 and
On Fri, 19 Jul 2013, Kwok Cheung Yeung wrote:
> Decode trap instructions during the handling of an EXCP_BREAK or EXCP_TRAP
> according to the current ISA mode.
>
> Signed-off-by: Kwok Cheung Yeung
> ---
> linux-user/main.c | 46 +++---
> 1 file changed, 4
On Mon, 29 Jul 2013, Maciej W. Rozycki wrote:
> > Decode trap instructions during the handling of an EXCP_BREAK or EXCP_TRAP
> > according to the current ISA mode.
> >
> > Signed-off-by: Kwok Cheung Yeung
> > ---
> > linux-user/main.c | 46 +
On Thu, 15 Aug 2013, Aurelien Jarno wrote:
> +/* Probe for MIPS32 instructions. As no subsetting is allowed
> + by the specification, it is only necessary to probe for one
> + of the instructions. */
> +#ifndef use_mips32_instructions
> +got_sigill = 0;
> +asm volatile(".se
On Thu, 15 Aug 2013, Aurelien Jarno wrote:
> > The MIPS32 instructions missing from Vr5500 are the EJTAG stuff (DERET
> > and SDBBP), JR.HB/JALR.HB (hmm, weird -- these are actually not guaranteed
> > to work on all MIPS32 chips either, e.g. the 4Kc didn't support these
> > encodings and trapp
setting Cause to 0x300 and
then Status to 0x201, and then making a few single steps, but that didn't
cause the interrupt exception to be taken for some reason. That does not
appear to be a problem with my change though. Perhaps there is a bug
elsewhere.
Signed-off-by: Maciej W. Ro
_libc_init_array+132>: lw v0,0(s1)
(gdb)
0x8000b46c in __libc_init_array ()
4: /x $ra = 0x8000b460
2: x/i $pc
=> 0x8000b46c <__libc_init_array+136>: lw ra,28(sp)
(gdb)
0x8000b470 in __libc_init_array ()
4: /x $ra = 0x8000891c
2: x/i $pc
=> 0x8000b470 <__libc_init_array+14
x80004d34 in _start ()
5: x/i $pc
=> 0x80004d34 <_start+380>: mtc0t1,c0_config
(gdb)
0x80004d34 in _start ()
5: x/i $pc
=> 0x80004d34 <_start+380>: mtc0t1,c0_config
(gdb)
0x80004d34 in _start ()
5: x/i $pc
=> 0x80004d34 <_start+380>: mtc0t1,c0_confi
The CP1 FIR register is read-only, ignore any write attempts from the GDB
stub.
Signed-off-by: Maciej W. Rozycki
---
Definitely obvious, please apply.
Maciej
qemu-mips-fir.diff
Index: qemu-git-trunk/gdbstub.c
===
--- qemu
fpu_init
setup, then proceeds to reinitialize all the CP0 registers...but not
FCR0."
I have verified this change with system emulation running the GDB test
suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated),
there were 55 progressions and no regressions.
Signed-off-b
diverging -- all
the hflags state is initialized in one place now.
Signed-off-by: Maciej W. Rozycki
---
This is effectively a follow-up to Nathan's FCR0 fix -- please apply.
Maciej
qemu-mips-hflags.patch
Index: qemu-git-trunk/target-mips/
ate the comment accordingly was missed and not
propagated. Here's an update to remove the obsolete and now misleading
comment.
Signed-off-by: Maciej W. Rozycki
---
Mostly obvious, please apply.
Maciej
qemu-mips16-jal.diff
Index: qemu-git-trunk/tar
rect to me, and the same
calculation is already used in exception_resume_pc applied to ordinary,
Debug and NMI exceptions. This code on the other hand applies to reset
exceptions and instruction restarts in the context of I/O.
Signed-off-by: Maciej W. Rozycki
---
Sent on behalf of Nathan, w
On Fri, 8 Jun 2012, Meador Inge wrote:
> > The problem was seen with the 24Kf MIPS32r2 processor in user emulation.
> > The new approach prevents system and user emulation from diverging -- all
> > the hflags state is initialized in one place now.
>
> I submitted a patch to fix this issue and
On Fri, 8 Jun 2012, Andreas Färber wrote:
> >>> The problem was seen with the 24Kf MIPS32r2 processor in user emulation.
> >>>
> >>> The new approach prevents system and user emulation from diverging -- all
> >>> the hflags state is initialized in one place now.
> >>
> >> I submitted a patch
On Mon, 9 Feb 2015, Peter Maydell wrote:
> >> I'm not sure if it's a good idea to change the meaning of linux-user
> >> qemu-mips64 and qemu-mips64el, this will cause unnecessary confusion in
> >> my opinion. I think we’d be better off leaving it consistent across QEMU
> >> versions.
> >
> > Well
On Wed, 7 Jan 2015, Alexander Graf wrote:
> diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
> index 7f74466..81db60f 100644
> --- a/target-ppc/fpu_helper.c
> +++ b/target-ppc/fpu_helper.c
> @@ -920,14 +923,16 @@ uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)
>
> farg.l
On Tue, 9 Dec 2014, Maciej W. Rozycki wrote:
> Index: qemu-git-trunk/target-mips/op_helper.c
> ===
> --- qemu-git-trunk.orig/target-mips/op_helper.c 2014-12-08
> 23:22:12.0 +
> +++ qemu-git-tr
On Thu, 19 Feb 2015, Leon Alrae wrote:
> > I think this deserves a better description as it is about the specific
> > case of an unaligned standard MIPS instruction fetch. Address Error
> > exceptions can also happen for other reasons: unaligned data accesses or
> > any accesses outside memor
On Thu, 19 Feb 2015, Leon Alrae wrote:
> > Surely these fp_status fields are simply implementation of the architectural
> > CSR registers?
> >
> > IMO you shouldn't store things related to TCG state, but always how the
> > architecture represents it. That way you're free to change the TCG
> > im
On Sat, 24 Jan 2015, manish tiwari wrote:
> I am new to QEMU and trying to attach gdb with qemu on powepc host.
>
> I have tried below options
>
> qemu-system-ppc -enable-kvm -nographic -m 512 -M ppce500 -cpu e500mc -gdb
> tcp::1234 -s -S -kernel uImage -initrd rootfs.ext2.gz -append
> "root=/de
I'm not sure if you need this, but just in case it helps anyhow.
Reviewed-by: Maciej W. Rozycki
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index e9d86b2..f33c10c 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -19103,6 +
On Mon, 26 Jan 2015, Leon Alrae wrote:
> Signed-off-by: Leon Alrae
> ---
Reviewed-by: Maciej W. Rozycki
Maciej
On Mon, 26 Jan 2015, Leon Alrae wrote:
> BadVAddr is supposed to capture the most recent address that caused
> the exception. Currently this is not happening as translation is not stopped
> and BadVAddr is updated with subsequent addresses.
>
> Signed-off-by: Leon Alrae
> ---
I think this dese
On Mon, 26 Jan 2015, Leon Alrae wrote:
> Signed-off-by: Leon Alrae
> ---
Enthusiastically:
Reviewed-by: Maciej W. Rozycki
However...
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 635192c..77d89be 100644
> --- a/target-mips/translate.c
>
On Thu, 29 Jan 2015, Leon Alrae wrote:
> > And do we want to have CP0C3_LPA set in the few templates that do in the
> > first place? AFAICT we don't really implement LPA so this bit will
> > confuse software. Of course implementing it would be another option, not
> > very complicated AFAICS,
On Fri, 30 Jan 2015, Peter Maydell wrote:
> > This patch series comprises changes to QEMU, both the MIPS backend and
> > generic SoftFloat support code, to support IEEE 754-2008 features
> > introduced to revision 3.50 of the MIPS Architecture as follows.
>
> Just to let you know that:
> (1) the
On Fri, 30 Jan 2015, Leon Alrae wrote:
> > @@ -760,6 +760,6 @@ static inline int float128_is_any_nan(fl
> >
> > /*
> > | The pattern for a default generated quadruple-precision NaN.
> >
> > *--
On Fri, 30 Jan 2015, Peter Maydell wrote:
> > Hmm, so perhaps my idea for a later improvement:
> >
> >> Eventually we might want to move the new inline functions into a
> >> separate header to be included from softfloat.h instead of softfloat.c,
> >> but let's make changes one step at a time.
>
On Sat, 31 Jan 2015, Peter Maydell wrote:
> >> > Hmm, so perhaps my idea for a later improvement:
> >> >
> >> >> Eventually we might want to move the new inline functions into a
> >> >> separate header to be included from softfloat.h instead of softfloat.c,
> >> >> but let's make changes one ste
On Tue, 3 Feb 2015, Thomas Schwinge wrote:
> > I think Thomas, being the writer of the majority of code comprising these
> > patches
>
> Too bad that Git doesn't allow for listing several authors. ;-)
I believe `Signed-off-by' serves this purpose:
"The Signed-off-by: tag indicates that the
On Thu, 5 Feb 2015, Peter Maydell wrote:
> > Index: qemu-git-trunk/fpu/softfloat-specialize.h
> > ===
> > --- qemu-git-trunk.orig/fpu/softfloat-specialize.h 2014-12-11
> > 22:42:41.128934304 +
> > +++ qemu-git-trunk/fpu/soft
formats.
> >
> > Therefore quieten any sNaN encountered in floating-point format
> > conversions, in the usual manner.
> >
> > References:
> >
> > [1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer
> > Society, IEEE Std
On Fri, 6 Feb 2015, Peter Maydell wrote:
> > What I think would make sense here is instead of say `float32_to_float64'
> > making a call to `float64_maybe_silence_nan' directly, we'd have a static
> > inline function or a macro called say `float64_convert_silence_nan'
> > invoked where the former
On Fri, 6 Feb 2015, Maciej W. Rozycki wrote:
> > >> I think this means that:
> > >> (1) we want to put handling of silencing the signaling NaNs
> > >> into the NaN conversion functions themselves (since it's
> > >> too late to do it corre
On Mon, 9 Feb 2015, Leon Alrae wrote:
> > Rework the MIPS ABIs and CPU emulations available according to the
> > following target list:
> >
> > - mips|mipsel -- 32-bit CPUs only, system and user emulation mode,
> >o32 user ABI,
> >
> > - mips64|mips64el -- 32-bi
On Mon, 9 Feb 2015, Leon Alrae wrote:
> > +if (info->elf_flags & EF_MIPS_NAN2008)
> > +env->active_fpu.fcr31 |=
> > +(1 << FCR31_NAN2008) & env->active_fpu.fcr31_rw_bitmask;
> > +else
> > +env->active_fpu.fcr31 &=
> > +~((1 <<
On Tue, 10 Feb 2015, Leon Alrae wrote:
> > These cases could be addressed by either replacing subtraction from 0.0
> > with multiplication by -1.0, or by tweaking the rounding mode as needed
> > temporarily. Given that the computational cost of multiplication is
> > uncertain and likely highe
On Wed, 11 Mar 2015, Alexander Graf wrote:
> > So if you know how to get working floppy disk with qemu-system-ppc64,
> > that would help me a lot in rejecting requests from libvirt folks :)
> > Thanks :)
>
> I don't think you want floppy disk emulation on -M pseries at all. In
> fact, you only ev
On Tue, 25 Nov 2014, Vasileios Kalintiris wrote:
> Add mips2-generic among CPU definitions for MIPS.
>
> Signed-off-by: Vasileios Kalintiris
> ---
> target-mips/translate_init.c | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff --git a/target-mips/translate_init.c b/tar
On Mon, 19 Jan 2015, Paolo Bonzini wrote:
> >> The reason I asked is simply because ISA devices never do MMIO (apart
> >> for the VGA window).
> >
> > You mean in the QEMU world? At least physical SCSI and Ethernet
> > adapters had a MMIO space for the onboard ROM.
>
> Uh right, ROMs count as MM
On Tue, 20 Jan 2015, Markus Armbruster wrote:
> >> diff --git a/target-mips/translate.c b/target-mips/translate.c
> >> index e9d86b2..8abc12b 100644
> >> --- a/target-mips/translate.c
> >> +++ b/target-mips/translate.c
> >> @@ -18729,6 +18729,7 @@ static void decode_opc(CPUMIPSState *env,
> >> Di
On Tue, 20 Jan 2015, Peter Maydell wrote:
> In this particular case, this part of the file is fine and the
> problem is simply that this patch as it stands introduces a single
> line (the one above) that's not indented correctly. The only fix
> required is to delete one space in the line added by
platforms (CONFIG_FULONG)
that are exclusively little-endian, 64-bit MIPS. Previously vt82c686.o
was pulled explicitly with obj-$(CONFIG_FULONG).
Signed-off-by: Maciej W. Rozycki
---
Hi,
Trivial stuff first, tougher later on. Compile-tested only, this
addresses a regression and should be
it.
Signed-off-by: Maciej W. Rozycki
---
I have a further change down the queue to clean up
`mips_cpu_gdb_read_register' and `mips_cpu_gdb_write_register' and make
them more consistent with respect to each other as far as the handling
of FP registers is concerned. For now please
CP1.FIR is read-only in hardware so gdbstub must respect it. We already
respect it for CTC1 instructions, so do it here too.
Signed-off-by: Maciej W. Rozycki
---
Not much to say about it here. Please apply.
Maciej
qemu-mips-fir.diff
Index: qemu-git-trunk/target-mips/gdbstub.c
roblem may have been easily missed because we have no hard-float
microMIPS CPU configuration present; in fact we have no microMIPS CPU
configuration of any kind present.
Signed-off-by: Maciej W. Rozycki
---
The latter problem is easily fixed though, with a patch I'll be sending
right awa
particular the
pipeline, stayed unchanged. Or to put it another way, the difference
between a 5K and a 5KE CPU corresponds to one between a 4K and a 4KE
CPU, except for the 64-bit rather than 32-bit ISA.
Signed-off-by: Maciej W. Rozycki
---
For the curious:
$ cat /proc/cpuinfo
system type
Define macros for CP0.Config3 and CP0.Config4 bits. These used to be
exhaustive as at MIPS32r3, but more bits may have been added since.
Signed-off-by: Maciej W. Rozycki
---
More can be added later on. For the time being, please apply.
Maciej
qemu-mips-config.diff
Index: qemu-git-trunk
Make the data type used for the CP0.Config4 and CP0.Config5 registers
and their mask signed, for consistency with the remaining 32-bit CP0
registers, like CP0.Config0, etc.
Signed-off-by: Maciej W. Rozycki
---
qemu-mips-config-int32_t.diff
Index: qemu-git-trunk/target-mips/cpu.h
, so these features are not marked,
making our support diverge from real hardware.
Signed-off-by: Sandra Loosemore
Signed-off-by: Maciej W. Rozycki
---
Hopefully we'll get the missing features sometime sooner rather than
later, they should not be difficult to add. Meanwhile having a
Enable vectored interrupt support for the 74Kf CPU, reflecting hardware.
Signed-off-by: Maciej W. Rozycki
---
qemu-mips-config-74k-vint.diff
Index: qemu-git-trunk/target-mips/translate_init.c
===
--- qemu-git-trunk.orig/target-mips
nfig3.DSP2P set or software won't detect its presence.
Signed-off-by: Maciej W. Rozycki
---
qemu-mips-config-dsp.diff
Index: qemu-git-trunk/target-mips/translate_init.c
===
--- qemu-git-trunk.orig/target-mips/translate_init.c
On Wed, 5 Nov 2014, Leon Alrae wrote:
> The actual microMIPS CPU definition is indeed a worthwile addition -
> thanks. It was on my TODO list to upstream such a CPU but I haven't got
> round to it.
You may still be able to contribute here, by adding microMIPS DSP CPUs.
Regrettably I wasn't abl
Signed-off-by: Maciej W. Rozycki
---
qemu-mips-translate-decode-opc-format.diff
Index: qemu-git-trunk/target-mips/translate.c
===
--- qemu-git-trunk.orig/target-mips/translate.c 2014-11-02 18:51:04.838001276
+
+++ qemu-git-trunk
Signed-off-by: Maciej W. Rozycki
---
qemu-mips-translate-init-format.diff
Index: qemu-git-trunk/target-mips/translate_init.c
===
--- qemu-git-trunk.orig/target-mips/translate_init.c2014-11-02
18:50:58.838990867 +
+++ qemu
Move the call to `update_fcr31' in `helper_float_cvtw_s' after the
exception flag check, for consistency with the remaining helpers that do
it last too.
Signed-off-by: Maciej W. Rozycki
---
I hope there's no question about this, please apply.
Maciej
qemu-mips-op-helper-cv
Remove the `FLOAT_OP' macro, unused since commit
b6d96beda3a6cbf20a2d04a609eff78adebd8859 [Use temporary registers for
the MIPS FPU emulation.].
Signed-off-by: Maciej W. Rozycki
---
qemu-mips-op-helper-float_op.diff
Index: qemu-git-trunk/target-mips/op_hel
more operations sprinkled across the file. Revert the mess by
moving FMA operations to a new ternary class inserted after the binary
class and move the misplaced unary and binary operations to where they
belong.
Signed-off-by: Maciej W. Rozycki
---
I hope there is no question about this either
On Wed, 5 Nov 2014, Leon Alrae wrote:
> > qemu-umips-cu1-ex.diff
> > Index: qemu-git-trunk/target-mips/translate.c
> > ===
> > --- qemu-git-trunk.orig/target-mips/translate.c 2014-10-27
> > 04:26:57.0 +
> > +++ qemu-g
4d34 in _start ()
5: x/i $pc
=> 0x80004d34 <_start+380>: mtc0t1,c0_config
(gdb)
0x80004d34 in _start ()
5: x/i $pc
=> 0x80004d34 <_start+380>: mtc0t1,c0_config
(gdb)
0x80004d34 in _start ()
5: x/i $pc
=> 0x80004d34 <_start+380>: mtc0t1,c0_config
(gdb
On Fri, 7 Nov 2014, Leon Alrae wrote:
> When I've been applying this patch to my mips-next candidate branch for
> 2.2 I realized that you haven't rebased it onto the recent version where
> MSA has been added to mips32r5-generic. Now I don't think that having
> DSP and MSA on one CPU makes sense, t
On Fri, 7 Nov 2014, Leon Alrae wrote:
> > I have been working with the current trunk, the change applies
> > correctly there AFAICT.
>
> 55a2201 commit added (1 << CP0C3_MSAP) to CP0_Config3 for
> mips32r5-generic which is not present on your patch.
Indeed, my mistake for some reason.
> > I
igned-off-by: Maciej W. Rozycki
---
Another change that has waited for too long, with the original
discussion archived here:
http://lists.nongnu.org/archive/html/qemu-devel/2012-06/msg01230.html
Resending with what hopefully is a better description and updated to
reflect the move of `cpu_io_reco
On Fri, 7 Nov 2014, Leon Alrae wrote:
> >> I was considering making mips32r5-generic less artificial and slowly
> >> evolve it towards some existing MIPS32R5 CPU, for example P5600 (which
> >> supports MSA, but doesn't support DSP ASE). Furthermore, none from the
> >> latest MIPS CPUs supports bot
s", pp. 210-211.
Signed-off-by: Maciej W. Rozycki
---
Leon,
Noticed in porting the next change I'm going to post. NB I have no
reasonable way to do run-time checks of an r6 configuration, so please
double check this works for you even though I believe it is obviously
correct; I did che
, and do not synchronise
the environment to evaluate side effects. We also write these registers
in the user emulation mode even though a real kernel presents them as
read only.
Signed-off-by: Maciej W. Rozycki
---
Hi,
I have verified the correct operation of this patch in the system
emulation
ves as an optimization as one op is produced in generated
code rather than two (again, unless `rs' is 0, where it doesn't change
anything).
Signed-off-by: Maciej W. Rozycki
---
This is rather obvious, but I also pushed it through full bare-iron GCC
regression testing with an o32 b
2013, Table 5.7 "FCSR Register
Field Descriptions", p. 81.
[2] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
MIPS64 Architecture", Imagination Technologies, Inc., Document
Number: MD00083, Revision 6.00, March 31, 2014, Table 6.7 "FCSR
Regist
On Wed, 12 Nov 2014, Andreas Färber wrote:
> Please consistently use "target-mips: " when that's what you're
> touching. (For hw/mips/ it's less consistent what to use.)
Sure. What about MIPS changes that span files contained within
target-mips/ and elsewhere? I have such changes in my queue.
On Wed, 12 Nov 2014, Peter Maydell wrote:
> > @@ -208,12 +206,12 @@ int cpu_load(QEMUFile *f, void *opaque,
> > MIPSCPU *cpu = mips_env_get_cpu(env);
> > int i;
> >
> > -if (version_id < 3) {
> > +if (version_id != CPU_SAVE_VERSION) {
> > return -EINVAL;
> > }
>
>
On Thu, 13 Nov 2014, Leon Alrae wrote:
> It might be a good idea to split these changes into separate patches to
> have more precise indication about touched subsystem (even though all
> the changes were done in MIPS context). For example "target-mips" and
> "linux-user" rather than just "mips".
Include CP0.Config2 through CP0.Config5 registers in the register dump
produced with the `info registers' monitor command. Align vertically
with the registers already output.
Signed-off-by: Maciej W. Rozycki
---
Hi,
This proved useful in debugging a CP0.Config3.ISAOnExc problem, fixed
rs another exception right away.
And then over and over again.
We already check the current setting of the CP0.Config3.ISAOnExc in
`set_hflags_for_handler' to set the ISA bit correctly on the exception
handler entry so it is the ability to set it that is missing only.
Signed-off-by: Maciej W.
Tighten ISA level checks down to MIPS II that many of our instructions
are missing. Also make sure any 64-bit instruction enables are only
applied to 64-bit processors, that is ones that implement at least the
MIPS III ISA.
Signed-off-by: Maciej W. Rozycki
---
Hi,
As usually with changes that
their semantics for stack accesses follows the architecture
specification. That in particular applies to user software run on
64-bit processors with the CP0.Status.UX bit clear where the address
space is wrapped to 32 bits.
Signed-off-by: Maciej W. Rozycki
---
Hi,
This change was also tested by
2013, Table 5.7 "FCSR Register
Field Descriptions", p. 81.
[2] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
MIPS64 Architecture", Imagination Technologies, Inc., Document
Number: MD00083, Revision 6.00, March 31, 2014, Table 6.7 "FCSR
Regist
Rewrite the FPU register access parts of `mips_cpu_gdb_read_register'
and `mips_cpu_gdb_write_register' for consistency between each other.
Signed-off-by: Maciej W. Rozycki
---
Hi,
This is the FPU register handling cleanup previously promised.
It was regression-tested by runni
Make CP0.Status writes made with the MTTC0 instruction respect this
register's mask just like all the other places. Also preserve the
current values of masked out bits.
Signed-off-by: Maciej W. Rozycki
---
Hi,
This should be obvious. Also quite obviously, we are missing a lot of
stu
Replace the 20Kc original MIPS64 ISA processor used for 64-bit user
emulation with the 5KEf processor that implements the MIPS64r2 ISA,
complementing the choice of the 24Kf processor for 32-bit emulation.
Signed-off-by: Maciej W. Rozycki
---
Hi,
For user emulation mode I think we want to
On Thu, 20 Nov 2014, Peter Maydell wrote:
> > For user emulation mode I think we want to default to the highest ISA
> > level supported, for maximum user flexibility. Currently the MIPS64r2
> > ISA is the highest 64-bit ISA we have a real processor support for so
> > use it and the 5KEf which is
On Mon, 24 Nov 2014, Leon Alrae wrote:
> All the patches up to this one have been applied to mips-next branch
> (available at git://github.com/lalrae/qemu.git), thanks. I'll go through
> the remaining soon.
Thanks. I am now back from a week's vacation and will continue posting
outstanding chan
On Tue, 2 Dec 2014, Leon Alrae wrote:
> > @@ -19276,6 +19276,10 @@ void mips_cpu_dump_state(CPUState *cs, F
> > env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
> > cpu_fprintf(f, "Config0 0x%08x Config1 0x%08x LLAddr 0x"
> > TARGET_FMT_lx "\n",
> > env->
On Tue, 2 Dec 2014, Leon Alrae wrote:
> > Please note that for this validation I'm using an artificial microMIPS
> > processor that also has an FPU implemented, so that our microMIPS FP
> > support is correctly validated too (I don't really know if there exists
> > any real microMIPS processor
Hi Blue Swirl,
On Wed, 5 Nov 2014, Maciej W. Rozycki wrote:
> Restore the order of helpers that used to be: unary operations (generic,
> then MIPS-specific), binary operations (generic, then MIPS-specific),
> compare operations. At one point FMA operations were inserted at a
>
bles-test.o] Error 1
happening when building QEMU with the `--enable-werror' configuration
option present. Report any failure from `fwrite'.
Signed-off-by: Maciej W. Rozycki
---
qemu-test-bios-tables-fwrite.diff
Index: qemu-git-
-off-by: Thomas Schwinge
Signed-off-by: Maciej W. Rozycki
---
qemu-mips-softfloat-status.diff
Index: qemu-git-trunk/target-mips/cpu.h
===
--- qemu-git-trunk.orig/target-mips/cpu.h 2014-12-02 16:29:15.0
+
+++ qemu-git
On Tue, 2 Dec 2014, Peter Maydell wrote:
> Is there ever a situation where you would want to
> resynchronise only one of these two things? If not,
> why not just have one function for synchronising
> softfloat state from the FCR?
Good point, I think these are safe and cheap enough to be always c
Reduce line wrapping throughout MSA helper macros by using a local float
status pointer rather than referring to the float status through the
environment each time. No functional change.
Signed-off-by: Maciej W. Rozycki
---
Hi,
The same float status applies across a single MSA operation
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