Include CP0.Config2 through CP0.Config5 registers in the register dump
produced with the `info registers' monitor command. Align vertically
with the registers already output.
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
---
Hi,
This proved useful in debugging a CP0.Config3.ISAOnExc problem, fixed
with the next patch. Eventually I think we should produce a complete
dump of CP0 registers, but for now this is an improvement. Ideally we'd
produce a suitable XML description so that GDB can access these
registers natively, but for that XML description support will have to be
implemented for bare-iron MIPS targets in GDB first.
Meanwhile, please apply.
Maciej
qemu-mips-info-regs-config.diff
Index: qemu-git-trunk/target-mips/translate.c
===================================================================
--- qemu-git-trunk.orig/target-mips/translate.c 2014-11-17 04:04:36.000000000
+0000
+++ qemu-git-trunk/target-mips/translate.c 2014-11-17 04:12:25.137964436
+0000
@@ -19276,6 +19276,10 @@ void mips_cpu_dump_state(CPUState *cs, F
env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
env->CP0_Config0, env->CP0_Config1, env->lladdr);
+ cpu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
+ env->CP0_Config2, env->CP0_Config3);
+ cpu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
+ env->CP0_Config4, env->CP0_Config5);
if (env->hflags & MIPS_HFLAG_FPU)
fpu_dump_state(env, f, cpu_fprintf, flags);
#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
