Define macros for CP0.Config3 and CP0.Config4 bits. These used to be
exhaustive as at MIPS32r3, but more bits may have been added since.
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
---
More can be added later on. For the time being, please apply.
Maciej
qemu-mips-config.diff
Index: qemu-git-trunk/target-mips/cpu.h
===================================================================
--- qemu-git-trunk.orig/target-mips/cpu.h 2014-11-02 01:08:26.527563002
+0000
+++ qemu-git-trunk/target-mips/cpu.h 2014-11-02 01:09:03.528200583 +0000
@@ -362,19 +362,34 @@ struct CPUMIPSState {
#define CP0C2_SA 0
int32_t CP0_Config3;
#define CP0C3_M 31
+#define CP0C3_BPG 30
+#define CP0C3_CMCGR 29
+#define CP0C3_IPLW 21
+#define CP0C3_MMAR 18
+#define CP0C3_MCU 17
#define CP0C3_ISA_ON_EXC 16
+#define CP0C3_ISA 14
#define CP0C3_ULRI 13
+#define CP0C3_RXI 12
+#define CP0C3_DSP2P 11
#define CP0C3_DSPP 10
#define CP0C3_LPA 7
#define CP0C3_VEIC 6
#define CP0C3_VInt 5
#define CP0C3_SP 4
+#define CP0C3_CDMM 3
#define CP0C3_MT 2
#define CP0C3_SM 1
#define CP0C3_TL 0
int32_t CP0_Config4;
int32_t CP0_Config4_rw_bitmask;
#define CP0C4_M 31
+#define CP0C4_KScrExist 16
+#define CP0C4_MMUExtDef 14
+#define CP0C4_FTLBPageSize 8
+#define CP0C4_FTLBWays 4
+#define CP0C4_FTLBSets 0
+#define CP0C4_MMUSizeExt 0
int32_t CP0_Config5;
int32_t CP0_Config5_rw_bitmask;
#define CP0C5_M 31
