On Thu, 5 Feb 2015, Peter Maydell wrote:
> > Index: qemu-git-trunk/fpu/softfloat-specialize.h
> > ===================================================================
> > --- qemu-git-trunk.orig/fpu/softfloat-specialize.h 2014-12-11
> > 22:42:41.128934304 +0000
> > +++ qemu-git-trunk/fpu/softfloat-specialize.h 2014-12-11
> > 22:43:02.128938514 +0000
> > @@ -103,6 +109,10 @@ inline float16 float16_default_nan(STATU
> > {
> > #if defined(TARGET_ARM)
> > return const_float16(0x7E00);
> > +#elif SNAN_BIT_IS_VARIABLE
> > + return STATUS(nan2008_mode)
> > + ? const_float16(0x7E00)
> > + : const_float16(0x7DFF);
> > #elif SNAN_BIT_IS_ONE
> > return const_float16(0x7DFF);
> > #else
>
> Ah, I see now what the previous patch was in aid of.
>
> (I hadn't realised that the 2008 rev of IEEE754 nailed down
> the SNaN/QNaN bit sense. That was always a dumb thing to have
> left impdef, so good news I guess.)
For MIPS the good side (or more likely intended) effect of the quiet bit
being set for sNaNs was you could preinitialise hardware registers in any
new FP context created to all-ones to have them trap uninitialised read
accesses for both single and double (and for that matter paired-single)
arithmetic. With the quiet bit being clear for sNaNs, there is no such a
single encoding available, you have to choose if you want to trap for
single (and paired-single) arithmetic only, double arithmetic only, or not
at all.
Maciej
