Fix an off-by-one error in `mips_cpu_gdb_write_register' for register
#72 that is handled further down in that function rather than here,
matching how `mips_cpu_gdb_read_register' handles it. This register
slot is a fake anyway, there's nothing in hardware that corresponds to
it.
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
---
I have a further change down the queue to clean up
`mips_cpu_gdb_read_register' and `mips_cpu_gdb_write_register' and make
them more consistent with respect to each other as far as the handling
of FP registers is concerned. For now please apply this obvious change.
Thanks.
Maciej
qemu-mips-fpreg72.diff
Index: qemu-git-trunk/target-mips/gdbstub.c
===================================================================
--- qemu-git-trunk.orig/target-mips/gdbstub.c 2013-07-29 11:23:07.048742983
+0100
+++ qemu-git-trunk/target-mips/gdbstub.c 2014-10-27 04:17:19.159003270
+0000
@@ -97,7 +97,7 @@ int mips_cpu_gdb_write_register(CPUState
return sizeof(target_ulong);
}
if (env->CP0_Config1 & (1 << CP0C1_FP)
- && n >= 38 && n < 73) {
+ && n >= 38 && n < 72) {
if (n < 70) {
if (env->CP0_Status & (1 << CP0St_FR)) {
env->active_fpu.fpr[n - 38].d = tmp;
