[USRP-users] Re: X410 SPI clock rate

; > If this is not the case, I can open an issue. BTW, I am using UHD 4.8. > Rob > > On Fri, Jun 27, 2025 at 11:17 AM Wade Fife wrote: > >> Rob, >> >> I don't know why you're seeing that behavior. The radio_clk does actually >> run at 122.88 MHz in you

[USRP-users] Re: X410 SPI clock rate

ng at 122.88 MHz with 2 samples per cycle. > > Rob > > On Thu, Jun 26, 2025 at 4:37 PM Wade Fife wrote: > >> Actually it looks like X410 and X440 use different clocks for the SPI >> core. Can you confirm which device you saw this on and what master clock >> rate you

[USRP-users] Re: X410 SPI clock rate

equation in the documentation is 245.76 MHz or 250 MHz, depending on your master clock rate. So: SPI_clk = 245.76 MHz / (divider + 1) What value was returned by usrp->get_radio_control()->get_rate()? Wade On Thu, Jun 26, 2025 at 2:41 PM Wade Fife wrote: > Hi Rob, > > I believe the u

[USRP-users] Re: X410 SPI clock rate

Hi Rob, I believe the underlying code that implements this is here: https://github.com/EttusResearch/uhd/blob/c354764c93b49c90be08958f942b9bcb7704cbd5/fpga/usrp3/lib/control/simple_spi_core.v#L182 It looks like the clock is inverted every divider+1 cycles, meaning divider+1 is half the SPI clock

[USRP-users] Re: X440 bus_clk

Hi Brian, In theory it should just work, but you have to be careful to change it in the right place, so that it gets updated everywhere, including outside of RFNoC. Otherwise, you could end up with clock mismatches in connected logic, which can cause all kinds of problems. Also, keep in mind that

[USRP-users] Re: X440 Reboot Takes A While

The 90 second timeout is a known issue, and it was recently fixed. With the next release, the USRP Hardware Daemon (MPM) service should shutdown immediately. But I'm not aware of it taking a long time after the service shuts down. In my experience, it reboots very quickly after the service shuts d

[USRP-users] Re: RFNoC CHDR DstEPID and Virtual Channels Clarification

I don't think static routing will help in your case. Stream endpoints are only for communicating over dynamic routes and the EPID is used for that routing. Wade On Mon, Apr 28, 2025 at 9:37 AM Brian Padalino wrote: > On Mon, Apr 28, 2025 at 10:33 AM Wade Fife wrote: > >>

[USRP-users] Re: RFNoC CHDR DstEPID and Virtual Channels Clarification

ta streams, then you'd want to use something like virtual channels or prepending your data with some kind of identifier. With many USRPs interconnected, you could have a lot more endpoints in theory. Wade On Mon, Apr 28, 2025 at 7:56 AM Brian Padalino wrote: > On Mon, Apr 28, 2025 at 8:47 A

[USRP-users] Re: RFNoC CHDR DstEPID and Virtual Channels Clarification

Right, up to 64 VCs per stream endpoint. Each stream endpoint only supports a single sequence number counter, so that single counter would be shared by all virtual channels. Wade On Sun, Apr 27, 2025 at 8:27 PM Brian Padalino wrote: > On Sun, Apr 27, 2025 at 8:44 PM Wade Fife wrote: >

[USRP-users] Re: RFNoC CHDR DstEPID and Virtual Channels Clarification

The EPIDs are only used by the stream endpoints. I think it will always be set to 0 when it is sent to your block, and anything you put in there will be ignored by downstream blocks. In theory, I suppose it could be used the way you described, but I think that would require pretty significant chang

[USRP-users] Re: X310: Changing DRAM Clock Frequency

Hi David, It is possible, but it can't be done from within RFNoC. The memory interface logic and clocking live outside of RFNoC. And you have to use the mem_clk to talk to this logic. The clock that's used for the memory is provided by the memory interface IP, so the easiest way to change it would

[USRP-users] Re: Monitor X310 health status

The API to read the FPGA temperature isn't in a release yet, but the register for the temperature is there. You can find an example of how to read it in this thread. https://lists.ettus.com/empathy/thread/FV3ZZ4C2EOBOOHKHKLAD66KN7INWNWX6 Wade On Wed, Apr 2, 2025 at 6:27 AM Martin Braun wrote:

[USRP-users] Re: [X440] Detected Rx sequence error and Receiver error: ERROR_CODE_TIMEOUT, continuing

Hi, I can see it's dropping a lot of packets from the S and D letters that are being printed. The 'D' means the host dropped an RX packet. The 'S' means the FPGA got a packet that did not have the right sequence number, which in practice means a packet was dropped. The rate you're testing is prett

[USRP-users] Re: rfnoc_image_builder error: trying to tool lock on already tool locked arc

% of the time, at least for me. If you find >> any tricks other than those previously mentioned please let me know. >> >> I'm going to do some digging once I'm not under deadline-pressure, as >> this issue is getting on my nerves somewhat. >> >> Kind

[USRP-users] Re: axi_mm io_signature issue

Hi Brian, I'm pretty sure that's a typo. Someone mixed 4096 with 8192. But it should not matter as long as the bus is big enough. The extra bits will be ignored and optimized out. Even 4096 is bigger than needed in most cases. There has been some work to have the image builder set these widths to

[USRP-users] Re: rfnoc_image_builder error: trying to tool lock on already tool locked arc

Hi David, I'm surprised that you're seeing it that frequently. The Ettus continuous integration tests build FPGAs regularly and from what I understand this issue is pretty rare there. This makes me wonder if there's something about the images you're building that causes this to reproduce more freq

[USRP-users] Re: Issue Upgrading UHD from 4.1 to 4.8 : [Error][MPDM] MPM major compat number missmatch

See here for instructions on how to update the filesystem on the device to the one that matches your UHD version. https://kb.ettus.com/USRP_X410/X440_Getting_Started_Guide#Updating_Filesystems Wade On Sun, Mar 2, 2025 at 3:18 PM Ofori Boateng, Joshua [E CPE] via USRP-users wrote: > Hi Álvaro,

[USRP-users] Re: x410 configuration

Yes, using one channel is supported. Wade On Tue, Feb 25, 2025 at 3:58 PM wrote: > Hello, > > We have done a project for gen3 x410 usrp 200MHz bandwidth 4channels > enabled. When we try to change configuration to 1 channel, tx/rx works but > we got strange behaviour in a custom part of design.

[USRP-users] Re: Build custom fpga image for x410

That does seem like a Vivado licensing issue. Vivado ML Enterprise is required, but no additional licenses should be required beyond what's included with Vivado. I don't know if there are any limitations of a trial license that would affect this. Make sure that the license is correctly installed an

[USRP-users] Re: X410 Front Panel GPIO to RFNoC

Hi Alex, I know that Ettus Research is aware of this and it's being looked at as a possible feature. In the current version of UHD, you still have to make manual changes to the FPGA to access the GPIO from RFNoC. The changes aren't particularly difficult, but it can be intimidating if you're not f

[USRP-users] Re: Build custom fpga image for x410

You can find information on how to build FPGA images in the user manual. Be sure to use the Vivado version and patches indicated for the UHD version you're using. The current version needs Vivado 2021.1 https://uhd.readthedocs.io/en/latest/md_usrp3_build_instructions.html X410 natively supports 2

[USRP-users] Re: X410 benchmark_rate underrun at 50MSps

cessfully (no underruns) with UHD version 3.14.1. > > > > Is there an issue with a newer UHD (4.6.0) and an older OS (CentOS 7.6)? > Are there any optimizations that are perhaps different on the older > CentOS-based system? > > > > Jeremy > > > > *From:* Wad

[USRP-users] Re: X410 benchmark_rate underrun at 50MSps

Hi Jeremy, This is a good reference of things you can try: https://kb.ettus.com/USRP_Host_Performance_Tuning_Tips_and_Tricks Also, I wonder if RT_RUNTIME_SHARE could be causing problems? You can find some info here on how to enable it: https://kb.ettus.com/Getting_Started_with_DPDK_and_UHD#Underr

[USRP-users] Re: RFNOC 4 equivalent of clear_tx_seqnum

RFNoC 4 tries to do this automatically at the start of a session. When UHD initializes a block, it will try to flush all of its FIFOs to clear any data from the previous session. There's no equivalent to clear_tx_seqnum. I suggest letting UHD do its thing and see if that's sufficient for your needs

[USRP-users] Re: x410/RFNoC xsim simulation support pertaining to rfnoc, x410, and system verilog.

Hi Andrew, All of the testbenches that have a Makefile should work with XSim except for the ones listed in this file: https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/tools/utils/testbenches.excludes And all of the testbenches that have a Makefile should work in ModelSim except for the

[USRP-users] Re: x410 RFNOC Endpooint YAML Configuration

Hi Andrew, This is true of all RFNoC images. The "ctrl" setting refers to whether or not that endpoint has a connection to the control crossbar, which is used for sending control packets (e.g., register reads/writes) to/from RFNoC blocks. Because you can send control packets to any RFNoC block fro

[USRP-users] Re: Error on using split stream and FFT rfnoc block.

With this FFT block, you need to set the SPP to match the FFT size for it to work correctly. I'm not very familiar with GNU Radio but I think there is an SPP parameter on the RX radio. I don't know how to set it for TX. Wade On Wed, Oct 23, 2024 at 5:45 AM Nidhi Panda wrote: > Hello, > > I am

[USRP-users] Re: Error on adding RFNoC BLOCK - FFT.

Hi Nidhi, In the YML file you have the same clock input on the FFT block driven from three sources. - { srcblk: _device_, srcport: ce, dstblk: fft0, dstport: ce } - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: fft0, dstport: ce } - { srcblk: _device_, srcport: radio, dstblk: fft0,

[USRP-users] Re: RFNoC Replay module (DRAM to PC)

Q1) Yes, only one channel is required. Each channel has both send and receive capabilities and you can use both simultaneously. However, note that sending and receiving between host and replay block, and between replay block and radio, simultaneously, would require two channels. For example, one ch

[USRP-users] Re: USRP-2974 FPGA core temperature

I don't have any data on what the expected spread is. But I suggest you double check that the fans are operating similarly to the other units and that air flow around the unit is not blocked in any way. Wade On Tue, Oct 1, 2024 at 4:14 AM wrote: > Hi Ettus Team > > I have a couple of USRP-2974

[USRP-users] Re: SPP, Burst Transmission and RFNoC AXI Data Signals

Hi Aditya, Each CHDR packet will be given to the block as an AXI packet, so TLAST asserts every S samples. At the end of a burst, the EOB flag in the header of the CHDR packet is asserted to indicate it's the last packet of the burst. Wade On Tue, Aug 13, 2024 at 8:08 PM Sathish, Aditya wrote:

[USRP-users] Re: Fwd: UHD 4.7 - Building X310_XG FPGA

IP generation issues tend to be caused by using the wrong Vivado version, or having stale files laying around from previous versions. Make sure you're using Vivado 2021.1 with the patch AR76780 installed. If you changed Vivado versions at some point, you may need to clean the repo to remove any sta

[USRP-users] Re: x310 Not Sending Jumbo Packets (>8000 bytes) as 1 Packet on 10GigE

You might need to make some tweaks to your system. Take a look at the suggestions here: https://kb.ettus.com/USRP_Host_Performance_Tuning_Tips_and_Tricks Wade On Mon, Jun 24, 2024 at 8:18 PM wrote: > Hi Wade, > > I am now receiving “U” instead of “L”. They don’t come out on the console > that o

[USRP-users] Re: Ettus KB: Missing CE clocks

Thanks for pointing that out! I'll make sure that gets updated. Thanks, Wade On Tue, Jun 25, 2024 at 12:52 PM Rohde, Zach (US 333G) via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello, > > > > I noticed in the RFNoC Frequency Asked Questions >

[USRP-users] Re: x310 Not Sending Jumbo Packets (>8000 bytes) as 1 Packet on 10GigE

For the first version can you try setting has_time_spec to false after the first packet is sent, and don't bother to set the time_spec on subsequent packets within a burst? The time_spec should really only be for the first packet. The radio will ignore the timestamp on the subsequent packets within

[USRP-users] Re: x310 Not Sending Jumbo Packets (>8000 bytes) as 1 Packet on 10GigE

Hi all, 8192 bytes is the maximum frame size supported by the FPGA, but that's including all headers. So the actual RF data payload that you can send is less than this, typically closer to 8000 bytes. I often set my SPP to 1996 out of habit since this is usually a pretty safe number with jumbo fra

[USRP-users] Re: RFNoC socket error on X410

One common thing that causes this error is having cables swapped. Normally, you need to connect the host computer port with 192.168.10.1 to the SFP port with 192.168.10.2 (and they should be on the same subnet), but if you mix them up then it'll sometimes let you ping, but more complex operations l

[USRP-users] Re: RFNoC FFT block on X410

Hi Sebastian, You might be using an old YAML file and tring to apply it to a new version of UHD. Take a look at the YAML file for the version of the FPGA closest to what you want. For example, here's the default X410 image in UHD 4.6: https://github.com/EttusResearch/uhddev/blob/UHD-4.6/fpga/usrp

[USRP-users] Re: Unable to Simulate RFNoC FFT Module in Questa/Modelsim

Sure, at this moment I'm using: Vivado v2021.1_AR76780 Model Technology ModelSim SE-64 vsim 2021.3 Simulator 2021.07 Jul 13 2021 Our CI pipelines appear to be using: ModelSim SE-64 2020.4 I know we've used PE, DE, and Questa as well, but I don't know for sure when we last tested this particular I

[USRP-users] Re: Unable to Simulate RFNoC FFT Module in Questa/Modelsim

Hmm. If the library path is correctly added in the modelsim.ini being referenced, then it should find it, or at least the error would be different. You could check the [Library] section of your modelsim.ini to make sure everything looks correct. As another option, have you tried "make modelsim" to

[USRP-users] Re: Unable to Simulate RFNoC FFT Module in Questa/Modelsim

Did you look through the simulation libraries that you built to see if xfft_v9_1_6 is in there? I'm wondering if it's not there or if ModelSim just can't find it. Take a look at the manual page if you haven't already: https://files.ettus.com/manual/md_usrp3_sim_running_testbenches.html Let's assu

[USRP-users] Re: Non-Unique Device MAC Address's After Mender F.S. Update

The MAC address should come from the EEPROM. You can run eeprom-dump on the device to see what MAC addresses are programmed in it. You can use eeprom-init to program the EEPROM. Run either with --help to see the syntax. https://github.com/EttusResearch/uhd/blob/master/mpm/tools/README.md I'm curi

[USRP-users] Re: question about X410 _d images and CHDR width

Hi Dario, The _d version is optimized for use with DRAM and the non-_d version is optimized for streaming to a connected host computer over 100 GbE. On the non-DRAM versions, the wider CHDR width gets applied to the stream endpoints, which connect to the host computer via 100 GbE. In testing we've

[USRP-users] Re: CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more evaluation cores that will cease to function after a certain period of time. This desig

Hi German, The critical warning sounds ominous but can be safely ignored. The licenses are included with Vivado, but Vivado gives the warning anyway. As long as you have a Vivado license, and a bitstream was generated, the 10 GbE IP should work fine. Wade On Thu, Dec 21, 2023 at 11:20 AM German

[USRP-users] Re: Error while running command "rfnoc_image_builder -y ./e310_rfnoc_image_core.yml"

The E310 has a very small FPGA, so fitting the replay block and DRAM logic is a challenge. You might be able to fit a single replay channel, but nothing else extra. If you're limiting the device to one channel, you might also be able to remove one of the radio channels and the corresponding stream

[USRP-users] Re: Error while running command "rfnoc_image_builder -y ./e310_rfnoc_image_core.yml"

Hi Muhammad, It says the design doesn't fit in the FPGA. Did you modify the YAML or FPGA code? If so, you may need to reduce what you're including. If not, maybe try building the unmodified FPGA: cd fpga/usrp3/top/e31x source setupenv.sh make E310_SG3 Thanks, Wade On Tue, Dec 12, 2023 at 9:05 

[USRP-users] Re: rfnoc_image_builder error with uhd4.6

Hi Enrico, The line numbers in the traceback don't seem to match UHD 4.6. Can you check if you maybe have different or multiple versions installed? And double check that the rfnoc_image_builder being called is indeed the version for UHD 4.6? For example, if you installed from source, double check

[USRP-users] Re: RFNOC TB

You would need to replace the code that writes to the DUT with code that reads from your file and writes your data instead. Similarly for the output, replace the code that checks the output with your own code to check the output and/or write it to a file. My guess is that your changes broke some as

[USRP-users] Re: RFNoC/MPM: No valid clock index given (63)

Thanks for reporting Zach. This will be fixed soon. Thanks, Wade On Wed, Nov 1, 2023 at 3:49 PM Rohde, Zach (US 333G) via USRP-users < usrp-users@lists.ettus.com> wrote: > I am trying the new UHD 4.6 X440 X4_200 image and I am running into this > error after updating the host UHD and flashing t

[USRP-users] Re: RFNOC TB

Yes, you can do that. Wade On Tue, Oct 10, 2023 at 7:19 AM wrote: > Hi every one, > > > I would like to use the rfnoc testbench but with my own signals and remove > this condition: > > > `ASSERT_ERROR( > > sample_out == sample_in, > > $sformatf("Sample %4d, received 0x%08X, expected 0x%08X", >

[USRP-users] Re: X440 at lower sample rates

Hi Dario, There are other differences in the FPGA code as well, since X440 is designed for higher rates and channel counts. For example, the X440 doesn't have additional DDCs/DUCs in the FPGA fabric. I think the manual page does a pretty good job of summarizing the differences. https://uhd.readth

[USRP-users] Re: ettus x410, Device is in bad state error

Hi Joe, Update the filesystem on the X410 to match the UHD version you're using on your host computer (and the bitstream you're trying to load): https://kb.ettus.com/USRP_X410_Getting_Started_Guide#Updating_Filesystems Thanks, Wade On Wed, Sep 6, 2023 at 12:30 PM wrote: > Hello, > > > I am c

[USRP-users] Re: Specifications of host computer for 100 Gb/s streaming with x410

Yes, one QSFP gives you one 100 GbE port. So there are two 100 GbE ports with the X410_CG_400 image. Regarding other considerations, see the expected data throughput rates in that same link. Streaming performance is generally limited by the host computer. Wade On Tue, Aug 29, 2023 at 3:36 PM wro

[USRP-users] Re: Specifications of host computer for 100 Gb/s streaming with x410

There are some general recommendations here: https://kb.ettus.com/X410#100_Gigabit_Ethernet The CPUs listed there are a bit old now. High single-thread CPU performance is important. Having several CPU cores dedicated for streaming is important too, but you can only use so many cores for streaming,

[USRP-users] Re: X410 FPGA build failure with UHD-4.4

Oh, interesting. I'd like to understand why it doesn't work for some people. This FPGA gets built quite regularly by myself and others without this issue. Wade On Fri, Aug 25, 2023 at 9:53 AM wrote: > Hello, > > The undefined *RFNOC_EDGE_TBL_FILE* macro is a typical error when you try > to buil

[USRP-users] Re: EXTERNAL: Re: X410 FPGA build failure with UHD-4.4

y what's going on there. > > Also, the "dev_config.json" file was missing from the x400 folder, not > sure if that's another generated file, or just missing from the branch. I > copied that from the x300 folder. > > Thanks, > > Ryan > > ---

[USRP-users] Re: X410 FPGA build failure with UHD-4.4

Hi Ryan, What was the problem/error message that suggested that folder wasn't being pulled in properly? The "syntax error" implies that the `RFNOC_EDGE_TBLE_FILE definition isn't being set correctly, but the makefile should pass that in based on the target you're building. Did you make modificati

[USRP-users] Re: Fatal: Timeout: Test "Test passing through samples" time limit exceeded

A testbench timeout is intended to prevent the test from waiting forever for something that's not working. So if it's timing out, it's either because the timeout is too short or because the thing it's waiting for is not happening. Try searching for the timeout message text to see where the timeout

[USRP-users] Re: Component fpga is too new for X410

The MPM software on your device is older than the FPGA you're trying to use. Because you're using master, they haven't published updated filesystems with the new MPM yet, but there will be a release candidate very soon for UHD 4.5 you could try. Wade On Tue, Aug 22, 2023 at 10:20 AM Zacharias M K

[USRP-users] Re: USRP X410 and PCIe connection

PCIe using the iPass+ zHD connectors is not supported on X410 with UHD. Like Marcus said, there's no software support in UHD for it. It is only supported with NI LabVIEW using the NI-USRP driver. Wade On Mon, Aug 21, 2023 at 11:36 AM Marcus D. Leech wrote: > On 21/08/2023 12:24, Paul Atreides w

[USRP-users] Re: Overflows with CHDR_W = 128 on x410

That would be the radio reporting the overflow then. So, it sounds like your gate causes data to back up into the radio where it eventually ran out of room. Increasing the PYLD_FIFO_SIZE makes more space for data to buffer up, increasing the time before an overflow would occur Wade On Fri, Aug 18

[USRP-users] Re: Overflows with CHDR_W = 128 on x410

What was the error message or symptom that told you that you were getting an overflow? RFNoC has flow control throughout the datapath, so when things can't keep up, the pipe normally backs up into the radio and that's where the overrun occurs. In other words, when the radio receives a new sample bu

[USRP-users] Re: Overflows with CHDR_W = 128 on x410

You are correct about INGRESS_BUFF_SIZE. It's only used to buffer data that the stream endpoint receives from another endpoint (e.g., data sent from the host computer to a stream endpoint). There's no extra buffering in the sending stream endpoint. For normal RX where we stream to a host computer,

[USRP-users] Re: Overflows with CHDR_W = 128 on x410

If you are streaming data from the radio, then overflows are to be expected since 10 GbE can't keep up with 500 Msps. But that should happen with 64-bit CHDR as well. It doesn't matter how big the buffers are. If you are not using the radio, then overflows should not occur at all, since there's no

[USRP-users] Re: How to use Questa for simulation

What gives an error? What are you trying to simulate and how are you running the simulation? The last time I used Questa, I think I just added it to my path instead of ModelSim and it worked the same. Some additional changes might be needed if you want to use Visualizer with our Makefiles instead

[USRP-users] Re: Overflows with CHDR_W = 128 on x410

Hi Joe, Did you change the chdr_width in the rfnoc_image_core YAML file and rerun rfnoc_image_builder on that file? Which version of UHD are you using to build the FPGA? Streaming over 10 GbE to 128-bit CHDR with 500 Msps radio isn't a use case we test, since 10 GbE can't keep up. Normally we wo

[USRP-users] Re: Xilinx Zynq 7020 SoC

The Zynq SoC on the E3xx/N3xx USRPs is a 7-Series Xilinx device, so you'll find it with the other Xilinx 7-Series documentation. Maybe this is what you're looking for? https://docs.xilinx.com/v/u/en-US/ug479_7Series_DSP48E1 Wade On Mon, Aug 14, 2023 at 6:34 PM Marcus D. Leech wrote: > On 14/08

[USRP-users] Re: What is the power socket on an Octoclock CDA-2990?

The connector on the Octoclock is a Switchcraft L722RA. I don't know the part number for the mating connector, but you might be able to find a compatible one using that as a reference. Wade On Wed, Aug 9, 2023 at 7:33 AM Royce Connerley via USRP-users < usrp-users@lists.ettus.com> wrote: > I ret

[USRP-users] Re: MPM major compat number mismatch even after updating FW to latest on X410

I think you checked out the wrong branch. Looking at your [INFO] statement, it says you're using a2a04e31, which is the latest commit on master. 5.2 is also the version you should get from the master branch. The "4.4" hasn't been updated on master yet because it's not released yet. Wade On Fri, A

[USRP-users] Re: Building Bitstream for USRP X410

ther I should upgrade or downgrade the Vivado version? > Also, I am holding a University License of Vivado, is it possible that IP > is not available for my license? > Thanks. > > Regards, > Arman > > > On Tue, Jul 25, 2023 at 7:04 AM Wade Fife wrote: > >> Hi, >>

[USRP-users] Re: Building Bitstream for USRP X410

Hi, What did you run to get this error? Which version of the UHD repo are you using? Building the FPGA requires a Vivado license, but all of the IP is included with Vivado. Assuming you have a working Vivado license, please ensure you have the correct version of Vivado installed for the version o

[USRP-users] Re: Custom RFNoC block: data throughput bottleneck

> Jernej Kokalj > > The blocks' location ( > https://git.gsi.de/p.niedermayer/exciter/-/tree/feedback_rfnoc/rfnoc-beam_exciter/fpga > ): > >- sources and simulation are inside the >folder rfnoc_block_feedback_controller >- the rfnoc_block_feedback_controller uses

[USRP-users] Re: RFNoC Image Builder: two problems with Vitis HLS

/sdr/uhd/fpga/usrp3/lib/ip/axi_hb31/Makefile.inc:20: > LIB_IP_AXI_HB31_TRGT] Error 1 > > make[1]: Leaving directory '/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx' > > make: *** [Makefile:90: N3X0_IP] Error 2 > > > > > > Other than that, commenting out the line

[USRP-users] Re: RFNoC Image Builder: two problems with Vitis HLS

00:06] Current task: Initialization +++ Current Phase: Finished > > [00:00:06] Process terminated. Status: Failure > > > > I will report back on your suggestion of commenting out the line ASAP. I > would be very happy to hear feedback from you regarding the errors/warnings > above in the

[USRP-users] Re: Custom RFNoC block: data throughput bottleneck

I suspect your logic isn't processing packets correctly. For example, maybe the sequence number is wrong on the output packets, or some other header information is incorrect. Or maybe your AXI-Stream handshake logic is wrong, causing you to miss samples. Or maybe TLAST isn't being asserted on the c

[USRP-users] Re: RFNoC Image Builder: two problems with Vitis HLS

Hi Luca, Can you try going into the uhd/fpga/usrp3/top/n3xx/ and running `make cleanall` and running the build again? You should not have had to manually upgrade IP unless there was some kind of mismatch somewhere. Perhaps you tried building first without the patch but didn't clean out the old IP

[USRP-users] Re: UHD 4.0 - Reading FPGA core temperature - USRP2974

Hi Marino, The register is there, but it sounds like we don't expose it through the API. This utility is out of date, but it can still be used to read the temperature value: ~/uhd/firmware/usrp3/x300$ python2 x300_debug.py --addr=192.168.10.2 --peek=0xA02C In that command, 192.168.10.2 is the IP

[USRP-users] Re: Control operation timed out with custom block

Hi Joe, This error message usually means that the host did a register read/write request but never got a response from the USRP. This might happen, for example, if a clock wasn't properly connected to the NoC shell. It could also be some kind of network issue (swapped cables, firewall, improperly

[USRP-users] Re: x410 TX issues

I believe the indicator light is ultimately driven by the RFNoC radio block. It turns on when it receives data packets to be transmitted. So if it doesn't turn on, that likely means no data is making it from the replay block to the radio block. Wade On Thu, Jun 8, 2023 at 9:19 AM wrote: > I had

[USRP-users] Re: x410 TX issues

Wow, I don't know why running it in the GUI would matter. You mentioned you did some customization in the Vivado GUI. Could that have something to do with it? I looked over your YAML and I noticed you have MEM_DATA_W on the Replay block set to 128 but you're building for the X410_X4_200 target whi

[USRP-users] Re: N2rt13HDRTExceptionE in Vivado 2021.1

It depends on the target, but normally if you repeat the same build you will get exactly the same results. I suggest you try the build seed option I mentioned in your other thread. This feature is intended to give you a different build result when you want one. I'm curious to know what target you'

[USRP-users] Re: vivado 2021.2

Hi Kevin, You could upgrade Vivado. It would take some work to update all the IP, and there's a chance that something might break. That error is pretty random, so even the slightest change can make it go away. If you're using UHD-4.4 then you can change the build seed. For example: make BUILD_SE

[USRP-users] Re: x410 TX issues

Did you test your code one one of the default images? That'd be a good way to confirm that you're using the replay block correctly. It could also be a simple mistake in the YAML. Maybe you could share your custom YAML to get another set of eyes on it? Did you add any custom logic that data is supp

[USRP-users] Re: X410 not powering on

Hi Arjan, I have not heard of this before. It should be as simple as connecting an appropriate AC cable to the X410 power supply brick, plugging the AC cable into the wall, then plugging the 6-pin power cable into the X410 and pressing the power button. If you haven't already, try disconnecting e

[USRP-users] Re: Remote Streaming UHD 4.4 on USRP-2974

Hi, On the USRP-2974 I thought "sfp1" on the FPGA was the port that goes to the internal NIC/CPU. Maybe try sfp0? You should be able to see the packets in wireshark if you run that on the other computer. Also, the activity lite on the USR-2974 should blink. Thanks, Wade On Thu, May 18, 2023 at

[USRP-users] Re: intel X710DA4 NIC card and breakout cable

This is the card Ettus sells for this product. It's the Intel X7A-DA2. https://www.ettus.com/all-products/10gige-kit/ For X410 cables, if you want to use 4 x 10 GbE, go to this link and click to view the accessories for X410. Look for the "QSFP28 To 4xSFP28 Breakout Cable, 1M". https://www.ni.co

[USRP-users] Re: x410 x4_200 connectivity question

I don't think that card supports 4 x 10 GbE. But suppose you used a card that does, or you used multiple 10 GbE cards to connect to all four 10 GbE ports on the X410, then you would set the args to "addr=192.168.10.2,second_addr=192.168.11.2,third_addr=192.168.12.2,fourth_addr=192.168.13.2". The st

[USRP-users] Re: PCIe NIC card connect to USRP-X410

Hi, Please see the recommendations in the following KB article: https://kb.ettus.com/X410#10_Gigabit_Ethernet https://kb.ettus.com/X410#100_Gigabit_Ethernet Wade On Tue, Apr 4, 2023 at 12:45 PM wrote: > Hello, > > What PCIe NIC cards are suggested to connect USRP-X410 through 10GbE and > 100G

[USRP-users] Re: Backpressure over Ethernet

It sounds like something isn't right. The streamers should automatically backpressure. That's how it works with the radio, and it should be the same for a custom block connected to stream endpoints. We have seen cases where host ethernet interfaces can't keep up when you start approaching the line

[USRP-users] Re: Using RAM in a OOT block

Hi Lorenzo, There might be a better way to design the RAM you want. 4096 samples is only 16 KiB, which you should be able to do with block RAM. Using DRAM seems like overkill for such a small amount of data. For example, the DRAM IP itself uses more than 16 KiB of buffers just to talk to the DRAM.

[USRP-users] Re: X410 Overflow with Custom FPGA

rate can match the clock rate. Wade On Wed, Mar 22, 2023 at 10:00 PM Brian Padalino wrote: > On Wed, Mar 22, 2023 at 10:40 PM Wade Fife wrote: > >> Hi Brian, >> >> Unfortunately, the DSP inside the current RFNoC DDC block processes one >> sample per clock cycle.

[USRP-users] Re: X410 Overflow with Custom FPGA

Hi Brian, Unfortunately, the DSP inside the current RFNoC DDC block processes one sample per clock cycle. So the maximum sample rate through the DDC is the same as the rate of the clock you provide to the ce clock input. With the 400 MHz bitstreams, radio_2x is 245.76 MHz. Because this is below th

[USRP-users] Re: RFNOC module sending back (or receiving) data in the wrong order

You could swap the bytes in your block, or swap them in software on the host. The data gets rearranged by the streamer depending on the data type configured (e.g., sc16) and the endianness of the host machine. Wade On Tue, Mar 7, 2023 at 2:45 AM Vermeulen, Bas (Consultant) via USRP-users < usrp-u

[USRP-users] Re: USRP X410 + QSFP28 network adapter from intel

Hi Piotr, I don't know of anyone who has tried that card specifically for 10 GbE, but Intel cards in general are commonly used with USRPs for 10 GbE. However, the Intel cards are not recommended for 100 GbE on X410. See here for the recommended cards and cables which has been tested and validated

[USRP-users] Re: USRP E320 DMA

Hi Yasir, Maybe you could add another RFNoC CHDR port to your block just for streaming the parameter data. So it would have a dedicated streamer separate from the one used for ADC data. Wade On Fri, Feb 17, 2023 at 2:53 AM Yasir Özçalık wrote: > Hi everyone, > I have a problem with DMA. I am t

[USRP-users] Re: X310 - All LEDs are off

Hi Ali, I wonder if the FPGA is not coming up. I'm not sure what the LEDs do in that case and I don't have a device handy to check. You could try this recovery procedure to see if that fixes the problem. https://kb.ettus.com/X300/X310_Device_Recovery If not, the device may be damaged. Wade On

[USRP-users] Re: benchmark_rate throws error

Hi Joe, The error you're getting basically means it can't communicate with the FPGA on the N320. It's sending a packet to the device, but it's not getting the response packet it expects. So it could be a network configuration issue, a cabling issue, maybe a firewall issue, or something else that's

[USRP-users] Re: Block controller hangs in testbench

Hi Joe, You could try stepping through the testbench code in the simulator to see where it's hanging, or look at your block's signals in the simulation to see what it does with the write. Make sure it behaves the same as one of the register writes in a working testbench. Perhaps a reset signal is

[USRP-users] Re: Module not found when creating OOT module

My initial guess was that the module in rfnoc_block_trigger.v wasn't named rfnoc_block_trigger. Vivado says it found the file "rfnoc_block_trigger.v" but not the module named "rfnoc_block_trigger". Or perhaps there was something else wrong with the module that caused it to not compile? But then I d

[USRP-users] Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked

ivado project I used to import the > xci files for updating. Maybe there is a better way to open the .xci > without creating a new project? > > Thanks, > Lorenzo > > -- > *From:* Wade Fife > *Sent:* Thursday, February 2, 2023 7:37 PM >

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