Hi Andrew, All of the testbenches that have a Makefile should work with XSim except for the ones listed in this file: https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/tools/utils/testbenches.excludes
And all of the testbenches that have a Makefile should work in ModelSim except for the ones listed in this file: https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/tools/utils/modelsim.excludes There aren't specific constructs I'm aware of in the code that aren't supported by XSim. Most of the testbenches were written for one simulator or the other, and not always ported to the other simulator when it didn't just work as written. In some cases that might be because XSim didn't implement something correctly, but it could also be because of normal differences between simulators (e.g., non-deterministic execution of processes). It depends on the testbench. In general, if you want to know what constructs are supported by XSim, check out UG900, the Vivado Design Suite User Guide for Logic Simulation. Thanks, Wade On Fri, Dec 20, 2024 at 6:03 AM Andrew D <sciensfpga...@gmail.com> wrote: > Is there documentation that declares which simulations are not supported > by xsim? I have used build.py to produce modules.json. I also found a git > issue that states the qsfp wrapper simulation is not supported for xsim. > Can you provide any details on the system verilog constructs that are > utilized within the codebase that are incompatible with xsim? > > Thank you, > Andrew > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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