Hi Brian, In theory it should just work, but you have to be careful to change it in the right place, so that it gets updated everywhere, including outside of RFNoC. Otherwise, you could end up with clock mismatches in connected logic, which can cause all kinds of problems. Also, keep in mind that it will be harder to meet timing with a higher clock rate, so it's much more likely you'll see timing errors.
For X440, I think the right spot to change it is here: https://github.com/EttusResearch/uhd/blob/UHD-4.8/fpga/usrp3/top/x400/x4xx.sv#L433-L434 and https://github.com/EttusResearch/uhd/blob/UHD-4.8/fpga/usrp3/top/x400/x4xx.sv#L438-L439 Change it from clk_200 to using ce_clk. You'll also need to create the equivalent ce_clk_rst in the same way clk200_rst was created, but using ce_clk instead of clk200. Wade On Tue, May 6, 2025 at 5:31 PM Brian Padalino <bpadal...@gmail.com> wrote: > I'm looking to save some RFNoC resources by slimming down the CHDR > interface to be 128-bits for my block and, possibly, universally. > > I see the CHDR_W as well as the BLOCK_CHDR_W parameters, but I also see > the bus_clk is set to 200 MHz. > > The current 200 MHz CHDR clock @ 128-bit wide interface is slightly too > slow for my sample rates, but 266 MHz (CE clk) could potentially work. > > Is there anything I should be wary of if I want to change the bus_clk to > be the CE CLK instead of the 200 MHz clock using a 128-bit CHDR interface? > > Thanks, > Brian > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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