The EPIDs are only used by the stream endpoints. I think it will always be set to 0 when it is sent to your block, and anything you put in there will be ignored by downstream blocks. In theory, I suppose it could be used the way you described, but I think that would require pretty significant changes in both UHD and in the FPGA.
Could you use two stream endpoints instead to double the number of virtual channels? Thanks, Wade On Thu, Apr 17, 2025 at 11:38 PM Brian Padalino <bpadal...@gmail.com> wrote: > I have a design for an X440 that wants to have 128 virtual channels for > each of the ports of a 4-port block. > > The VC field in the header is only 6 bits, but the DstEPID is 16 bits. > > Is there some way to let the endpoint number be shifted up in the DstEPID > and pass through the bottom 7 bits? I'm using the chdr_to_axis_pyld_ctxt to > separate it out, but the DstEPID always seems to be 0 at least in my > testbench. It seems like maybe the EPID is dynamically assigned during some > type of configuration stage? > > I guess the other part of this is how I might be able to craft a CHDR > packet on the UHD side of things to send it down to my block. > > Can a block have multiple DstEPID's assigned to it? > > If there is another way I could get the 128 virtual channels per RFNoC > block port, please let me know. I am very much open to suggestions. > > Thanks, > Brian > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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