> On Jul 13, 2015, at 8:35 AM, Jay Jaeger wrote:
>
> Another alternative would be to build a machine up from a Field
> Programmable Gate Array (e.g., the Digilent Nexys2 FPGA development
> board). I recently completed an effort doing that for a 12 bit machine
> we designed and built in a logic/
>
> Date: Mon, 13 Jul 2015 01:52:09 -0400
> From: "Kip Koon"
> Subject: RE: PDP-12 at the RICM
>
> Hi Michael,
> I would be most interested in finding out more about this effort. Do you
> have ongoing pictures documenting this effort? I'd love to have a PDP 8,
> 11, 12 someday, but I don't have
>
> Date: Sun, 12 Jul 2015 16:10:10 -0500
> From: Jay Jaeger
> Subject: Re: PDP-12 at the RICM
>
> BTW, if there are particular cards you need / are bad, in addition to
> the actual PDP-12, I have the backplanes and cards for a 2nd one, so if
> you need something, we could probably work something
Thanks, yes you are right. And it is fixed now. Would have been more
easy with the schematics on hand.
But the 510 does not seem to start, may be the mini test program i have
(to boot from terminal) only works with the model 210 and not with the
510. (http://basicfour.de/cpu/small/index.html)
Hi,
I have a bunch of PCB's from a HP3000 series 52 computer. Is some one
interested in those?
The machine itself was still working when it was taken out of service in
the late 1990's. No guaranties are given though.
The location is in south of Sweden, but I'll guess I can pack them and
send the
I'm not even sure what the machine is. Can you give
a little more information on what it is?
Dwight
> Subject: Re: Linear Power Supply (Conversion Equipment Corp) from a basic
> four 510
> To: cct...@classiccmp.org
> From: a...@ardiehl.de
> Date: Mon, 13 Jul 2015 18:28:56 +0200
>
> Thanks, yes
On 7/13/2015 4:59 PM, Michael Thompson wrote:
>> Date: Mon, 13 Jul 2015 01:52:09 -0400
>> From: "Kip Koon"
>> Subject: RE: PDP-12 at the RICM
>>
>> Hi Michael,
>> I would be most interested in finding out more about this effort. Do you
>> have ongoing pictures documenting this effort? I'd love t
It is the follow on to the Microdata 1600 that Basic four used in its
first business machines.
He has two machines and at least a disk for the system, I think.
Basic Four became MAI. They were noted for having a multi user basic
system for business very early on.
Also it survive(s) today wi
> -Original Message-
> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Paul
> Koning
> Sent: 13 July 2015 17:03
> To: General Discussion: On-Topic Posts
> Subject: Re: Reproducing old machines with newer technology (Re: PDP-12 at
> the RICM)
>
>
> > On Jul 13, 2015, at 8:
- Original Message -
From: "Dave G4UGM"
To: "General Discussion: On-Topic and Off-Topic Posts"
Sent: Tuesday, 14 July, 2015 8:58:09 AM
Subject: RE: Reproducing old machines with newer technology (Re: PDP-12 at the
RICM)
...
My next project is likely to be the Ferranti Pegasus which
> From: Jay Jaeger
> I am going to attempt to do the same for IBM's 1410 computer - a really
> big effort.
Now, the IBM machine you (or someone) should _really_ do is the IBM Stretch
(7030); although judged a commercial failure at the time, in retrospect it's
clearly one of the most g
> From: Rich Alderson
> Changing from PDP-8 operation to LINC operation was a matter of a
> physical switch.
Err, not according to the "Small Computer Handbook" (1967 Edition), which
covers the LINC-8 in detail - at least, as I understand it? See, for instance,
pg. 307 "A LINC HALT in
Seconded; I was just leafing through "A DEC view of hardware systems
design" again last week and I had noticed that footnote and was wondering
myself ... the PDP-3 must be the rarest of them all :O I wonder if there
are any surviving leftovers?
Best,
Sean
On Tue, Jul 14, 2015 at 1:04 AM, Paul A
> On Jul 14, 2015, at 7:53 AM, Noel Chiappa wrote:
>
>> From: Jay Jaeger
>
>> I am going to attempt to do the same for IBM's 1410 computer - a really
>> big effort.
>
> Now, the IBM machine you (or someone) should _really_ do is the IBM Stretch
> (7030); although judged a commercial failure at
> On Jul 13, 2015, at 8:52 PM, Johnny Billquist wrote:
>
> On 2015-07-13 21:16, Rich Alderson wrote:
>> ...
>
>> [2] With memory management, 18 or 22, in 16-bit segments. Late models could
>> use separate instruction and data segments, for a total of 128KB in use
>> at
>> one time.
>
> -Original Message-
> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of ANDY HOLT
> Sent: 14 July 2015 10:20
> To: General Discussion: On-Topic and Off-Topic Posts
> Subject: Re: Reproducing old machines with newer technology (Re: PDP-12 at
> the RICM)
>
>
> - Or
My work has been using structural models, at the gate level, in VHDL
(Verilog would be fine, too, of course). Individual components (for
example, a piece of an IBM SMS card, or in my existing case, gates made
available to student engineers that were actually individual
gates/chunks of DTL chips) g
Actually, the automated design tools will automatically flag wired or /
wired and, because they result in tying the outputs of multiple
"drivers" together.
BTW, my next project for this kind of thing is intended to be the IBM
1410. Quite a challenge. I expect it will probably take me 2-3 years
On 7/14/2015 9:46 AM, Jay Jaeger wrote:
My work has been using structural models, at the gate level, in VHDL
(Verilog would be fine, too, of course). Individual components (for
example, a piece of an IBM SMS card, or in my existing case, gates made
available to student engineers that were actual
On 7/13/2015 10:02 AM, Paul Koning wrote:
A different approach is to reproduce the actual logic design. FPGAs
can be fed gate level models, though that’s not the most common
practice as I understand it. But if you have access to that level
of original design data, the result can be quite accur
> On Jul 14, 2015, at 11:46 AM, Jay Jaeger wrote:
>
> ...
> Using the structural / gate level techniques, one does run into some
> issues, most of which have (or will probably have) solutions:
>
> 1) R/S latches composed of gates in a combinatorial loop. The problems
> this causes are several
> On Jul 14, 2015, at 12:23 PM, ben wrote:
>
> On 7/13/2015 10:02 AM, Paul Koning wrote:
>
>> A different approach is to reproduce the actual logic design. FPGAs
>> can be fed gate level models, though that’s not the most common
>> practice as I understand it. But if you have access to that l
On 7/14/2015 10:29 AM, Paul Koning wrote:
On Jul 14, 2015, at 12:23 PM, ben wrote:
On 7/13/2015 10:02 AM, Paul Koning wrote:
A different approach is to reproduce the actual logic design.
FPGAs can be fed gate level models, though that’s not the most
common practice as I understand it. But
I'm missing something in this discussion, I think.
HDL's (take your pick) are just programming languages like FORTRAN or C
with different constraints. What's the point of going to all the
trouble of doing an FPGA implementation of a slow old architecture, when
pretty much the same result coul
> On Jul 14, 2015, at 1:17 PM, Chuck Guzis wrote:
>
> I'm missing something in this discussion, I think.
>
> HDL's (take your pick) are just programming languages like FORTRAN or C with
> different constraints. What's the point of going to all the trouble of doing
> an FPGA implementation of
> -Original Message-
> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Chuck
> Guzis
> Sent: 14 July 2015 18:17
> To: gene...@classiccmp.org; discuss...@classiccmp.org:On-Topic and Off-
> Topic Posts
> Subject: Re: Reproducing old machines with newer technology (Re: PDP-12
On 7/14/2015 11:17 AM, Chuck Guzis wrote:
I'm missing something in this discussion, I think.
HDL's (take your pick) are just programming languages like FORTRAN or C
with different constraints. What's the point of going to all the
trouble of doing an FPGA implementation of a slow old architectur
> On Jul 13, 2015, at 8:52 PM, Johnny Billquist wrote:
> ??? What segments??? The PDP-11 have a plain simple page table. No
> segments anywhere in sight. And each page is 8K.
I know the processor handbook calls them 'pages', but I can't think of any
other machine where pages are vari
> From: Paul Koning
>> I have a hard time coming up with other machines with the same level
>> of impact/influence, in terms of CPU internal architecture. Maybe
>> Atlas, or the 801?
> CDC 6600, of course.
I guess I don't know the 6600 that well (I have the book, and have ski
On 07/14/2015 10:35 AM, ben wrote:
I've run the Cyber emulator as well as various SIMH emulators from time
to time, but it's just not the same as the real thing--it's not even
remotely the same.
You can still the old computer blinking lights movie props.
On a Cyber? What blinking lights? P
Determinism. Unless you run your software simulator bare-metal - which
most aren't - cycle accuracy is always a race. Before you say modern
processors are 100,000 times faster than emulated ones - so just spin
wait until the next virtual time tick, that is always a moving ratio or
opportunity fo
Hello Everybody
In the course of doing the artwork for 8/e
type B I have turned up some more variations.
The list now looks like this:
1. Switch position markings
2. Line round switch area
3. The EMA title block isolated from the other titles
4. Lines between groups o
On 07/14/2015 10:55 AM, Noel Chiappa wrote:
I guess I don't know the 6600 that well (I have the book, and have skimmed it
in the past). What are the novel features in the 6600 that were widely
adopted by other machines? (I listed the Atlas because of paging, and the 801
because of RISC.)
There
On 07/14/2015 11:14 AM, Alan Hightower wrote:
Determinism. Unless you run your software simulator bare-metal - which
most aren't - cycle accuracy is always a race. Before you say modern
processors are 100,000 times faster than emulated ones - so just spin
wait until the next virtual time tick,
> On Jul 14, 2015, at 1:55 PM, Noel Chiappa wrote:
>
>> From: Paul Koning
>
>>> I have a hard time coming up with other machines with the same level
>>> of impact/influence, in terms of CPU internal architecture. Maybe
>>> Atlas, or the 801?
>
>> CDC 6600, of course.
>
> I guess I don't know
Back at a more general level. To my way of thinking what Bob Supnik did
in software can be extended by producing a hardware replica vehicle for
his code to give the illusion that the original system has been
recreated. A sort of machine Turing test if you will.
Rod Smallwood
/
/
/On 14/07/20
Hi Rod,
Any chance I could commission you to do an Altair 8800 panel?
The silkscreen has almost completely worn off on mine, but I have a
high-quality scan of a good one.
-Tom
On 14 July 2015 at 19:20, Rod Smallwood
wrote:
> Hello Everybody
> In the course of doing the
Kind reader
I have two manuals labelled STSC APL*PLUS System for VAX VMS: User's
Manual and Reference Manual which were sent to me a number of years ago
as paper copies - I now have the ability to easily scan these into PDF
format.
Would these be of interest to anyone? There is a PC version ar
Hi folks,
I'm looking to buy at whatever price is fair a GRiD Compass (Not the DOS
based ones) computer of any model-- and perhaps condition- as I may be able
to repair
I recently missed an ebay auction, which was sad.
Let me know,
Thanks,
- Ian
-
Background.
About a year or so, I purch
> On Jul 14, 2015, at 2:42 PM, Rod Smallwood
> wrote:
>
> Back at a more general level. To my way of thinking what Bob Supnik did in
> software can be extended by producing a hardware replica vehicle for his code
> to give the illusion that the original system has been recreated. A sort of
>
> That sounds like a bug in the original. If you have a set of flops clocked
> by some signal, and it matters that the
> outputs don’t all change at the same time, then the original wasn’t reliable
> either.
It is very poor design, and not something that I would do, but it certainly was
done
> On Jul 14, 2015, at 3:27 PM, tony duell wrote:
>
>
>> That sounds like a bug in the original. If you have a set of flops clocked
>> by some signal, and it matters that the
>> outputs don’t all change at the same time, then the original wasn’t reliable
>> either.
>
> It is very poor desig
> ...I/O processors.
I do not think you can claim that the 6600 I/O processors were all
that new. Many (most?) of the 1960s mainframes before the 6600 had
channel controllers.
--
Will
>
> I would modify that: if you take an existing design created by someone who
> doesn’t think about delay
> differences, then the FPGA version won’t work. Consider the 6600: at the
> speeds involved, you can’t
> design in that sloppy fashion. So there are multi phase clocks everywhere,
> w
> On Jul 14, 2015, at 3:55 PM, William Donzelli wrote:
>
>> ...I/O processors.
>
> I do not think you can claim that the 6600 I/O processors were all
> that new. Many (most?) of the 1960s mainframes before the 6600 had
> channel controllers.
Sure, but channel controllers and PPUs are very diff
On 07/14/2015 12:55 PM, William Donzelli wrote:
...I/O processors.
I do not think you can claim that the 6600 I/O processors were all
that new. Many (most?) of the 1960s mainframes before the 6600 had
channel controllers.
Perhaps not, but they were unique in their implementation (one "logic
Anyone contemplating dealings with Mr. Landon should check Google and
archives of this mailing list.
He's a thief.
* drlegendre . [150713 21:42]:
> Sent you a private email, Steve. Let me know if you don't see it..
>
> On Mon, Jul 13, 2015 at 5:51 AM, Steven Landon wrote:
>
> > Clearing out m
On 07/14/2015 10:29 AM, Paul Koning wrote:
The accuracy of the FPGA depends on the approach. If it’s a
structural (gate level) model, it is as accurate as the schematics
you’re working from. And as I mentioned, that accuracy is quite
good; it lets you see obscure details that are not documente
> Sure, but channel controllers and PPUs are very different beasts. You can’t
> run your OS on a channel controller, which is exactly what Cray did on the
> 6600. Nor can you implement the entire operator user interface on a channel
> controller, as was done in the DSD PPU program.
Yes, I rea
On 7/14/2015 1:56 PM, tony duell wrote:
You are, of course, absolutely correct...
However, such designs are very few and far between. I will guess that if you
took just about any of the
discrete transistor or TTL-baased minis or desktops and fed the design straight
into an FPGA compiler then
Going all the way back to at least the IBM 7090, and presumably the 709,
though I have not actually checked. The B5000 had IO processors as well.
On 7/14/2015 2:55 PM, William Donzelli wrote:
>> ...I/O processors.
>
> I do not think you can claim that the 6600 I/O processors were all
> that new.
Hi Tom
I had thought somebody had done one (or it was part of a kit)
However I cant find
anything about it. So lets have a look at your scan.
Regards
Rod
On 14/07/2015 19:44, Tom Moss wrote:
Hi Rod,
Any chance I could commission you to do an Altair 8800 panel?
The silkscreen has
> > However, such designs are very few and far between. I will guess that if
> > you took just about any of the
> > discrete transistor or TTL-baased minis or desktops and fed the design
> > straight into an FPGA compiler then
> > it will not work.
>
> What machines were you thinking of?
I wou
Hi
Oscar Vermeulen managed to get an 8/I replica going using a
Raspberry Pi and Bob's code.
You do have to hook into the code of course. I want to do an 8/e the
same way.
Regards Rod
On 14/07/2015 20:25, Paul Koning wrote:
On Jul 14, 2015, at 2:42 PM, Rod Smallwood
wrote:
Back at a m
On 07/14/2015 02:05 PM, Jay Jaeger wrote:
Going all the way back to at least the IBM 7090, and presumably the 709,
though I have not actually checked. The B5000 had IO processors as well.
Again, you're missing the point. The system *starts* with a PPU and
loads the CPU up to run. OS was pre
> Again, you're missing the point.
This was a fairly specific CDC Cyber thing - not a widely adopted idea
in the industry, as was originally asked for.
The channel controller/director idea, on the other hand, was very
widely adopted.
--
Will
Hi Rod,
The only kit I'm aware of is Grant Stockly's. AFAIK he's not been replying
to emails for about five years. There's also Mike Douglas's Altair Clone,
but that panel won't fit.
Here's the scan:
http://www.vintage-computer.com/images/altairfrontpanelscan.jpg
Just to be clear, I'm only looki
Wow, Landon's still at it after 12 years?
You'd have thought he'd have a life by now...
On 14 July 2015 at 21:38, Todd Goodman wrote:
> Anyone contemplating dealings with Mr. Landon should check Google and
> archives of this mailing list.
>
> He's a thief.
>
> * drlegendre . [150713 21:42]:
> >
On 07/14/2015 02:53 PM, William Donzelli wrote:
Again, you're missing the point.
This was a fairly specific CDC Cyber thing - not a widely adopted idea
in the industry, as was originally asked for.
The channel controller/director idea, on the other hand, was very
widely adopted.
That's true-
On 2015-07-14 16:09, Paul Koning wrote:
On Jul 13, 2015, at 8:52 PM, Johnny Billquist wrote:
On 2015-07-13 21:16, Rich Alderson wrote:
...
[2] With memory management, 18 or 22, in 16-bit segments. Late models could
use separate instruction and data segments, for a total of 128KB in
On 2015-07-14 19:52, Noel Chiappa wrote:
> On Jul 13, 2015, at 8:52 PM, Johnny Billquist
wrote:
> ??? What segments??? The PDP-11 have a plain simple page table. No
> segments anywhere in sight. And each page is 8K.
I know the processor handbook calls them 'pages', but I can't
> That's true--but at the time, CDC's design made a huge amount of sense. The
> CPU was left to do what it did best--crunch numbers without the burden of
> managing the I/O activity and responding to interrupts. In that sense, the
> CPU was treated as more of a peripheral device. In fact, you co
It was thus said that the Great Johnny Billquist once stated:
>
> Yeah. Segment is something I usually associate with the solution done in
> the 8086 family, where you essentially have a segment register which
> gives the base, and then you work from there. Essentially all memory is
> one chunk
On 2015-07-15 01:02, Sean Conner wrote:
It was thus said that the Great Johnny Billquist once stated:
Yeah. Segment is something I usually associate with the solution done in
the 8086 family, where you essentially have a segment register which
gives the base, and then you work from there. Essen
The reason I choose to use VHDL (or Verilog), both of which really *are*
IEEE standards: future portability and broadness of access across
multiple manufacturer's devices in the future, and compatibility with
logic simulators.
The 1130 is more modern than the machines I am interested in. While
t
> On Jul 14, 2015, at 4:41 PM, Chuck Guzis wrote:
>
> On 07/14/2015 10:29 AM, Paul Koning wrote:
>
>> The accuracy of the FPGA depends on the approach. If it’s a
>> structural (gate level) model, it is as accurate as the schematics
>> you’re working from. And as I mentioned, that accuracy is
> The 1130 is more modern than the machines I am interested in. While
> there are still several 1401's our there in the wild I am aware of no
> IBM 1410's anywhere, unless IBM has one squirreled away somewhere.
OK, I am curious. Why the love for the 1410?
I do not know of any, either.
--
Will
On 7/14/2015 11:27 AM, Paul Koning wrote:
>
>> On Jul 14, 2015, at 11:46 AM, Jay Jaeger wrote:
>>
>> ...
>> Using the structural / gate level techniques, one does run into some
>> issues, most of which have (or will probably have) solutions:
>>
>> 1) R/S latches composed of gates in a combinator
On 07/14/2015 03:42 PM, William Donzelli wrote:
That's true--but at the time, CDC's design made a huge amount of sense. The
CPU was left to do what it did best--crunch numbers without the burden of
managing the I/O activity and responding to interrupts. In that sense, the
CPU was treated as mor
On 7/14/2015 12:17 PM, Chuck Guzis wrote:
> I'm missing something in this discussion, I think.
>
> HDL's (take your pick) are just programming languages like FORTRAN or C
> with different constraints. What's the point of going to all the
> trouble of doing an FPGA implementation of a slow old a
> On Jul 14, 2015, at 7:40 PM, Jay Jaeger wrote:
>
> On 7/14/2015 11:27 AM, Paul Koning wrote:
>> ...
>
>>>
>>> 3) Flip flops which are clocked from combinatorial signals. These tend
>>> to cause timing/glitch issues. For example, in one case the
>>> combinatorial output was a zero-check on
On 7/14/2015 2:27 PM, tony duell wrote:
>
>> That sounds like a bug in the original. If you have a set of flops clocked
>> by some signal, and it matters that the
>> outputs don’t all change at the same time, then the original wasn’t reliable
>> either.
>
> It is very poor design, and not s
On 7/14/2015 2:56 PM, tony duell wrote:
>>
>> I would modify that: if you take an existing design created by someone who
>> doesn’t think about delay
>> differences, then the FPGA version won’t work. Consider the 6600: at the
>> speeds involved, you can’t
>> design in that sloppy fashion. S
Sometimes it is fun to be a relative expert on an obscure branch of
knowledge that few people are even aware of.
I worked on one when I was a student, as an operator, programmer and
systems programmer. Tweaked its FORTRAN compiler to spit out text error
messages instead of just error codes. The
On Tue, Jul 14, 2015 at 3:28 PM, tony duell wrote:
> If you mean 6 different clock sources (i.e. clocks delayed from each other,
> etc) then that
> is not typical of a 1970s minicomputer in my experience.
IIRC, the KB11 processors used in the DEC 11/45 and 11/70 (and other
related systems) used
> IIRC, the KB11 processors used in the DEC 11/45 and 11/70 (and other
> related systems) used five "clocks delayed from each other" (more
> commonly known as clock phases).
IBM used this method as well on many of their machines.
--
Will
The 12-bit computer that I "translated" originally had *independent* 1
micro-second clocks in each of four racks. The processor derived a 3
micro-second clock from that, but also a second clock that was out of
phase with the CPU master clock, used to sync. signals coming in from
the other racks (w
Almost sounds like the CPU was kind of an "attached processor" - similar
to the way vector processors have been implemented by IBM and others.
On 7/14/2015 5:28 PM, Chuck Guzis wrote:
> On 07/14/2015 02:53 PM, William Donzelli wrote:
>>> Again, you're missing the point.
>>
>> This was a fairly spe
> From: Johnny Billquist
> While the pages are variable in length, each page starts at an 8K
> virtual address boundary.
Which is another difference between PDP-11 'pages', and real pages as used on
every other machine of the period which had virtual memory: normally, page
sizes were
On 07/14/2015 04:49 PM, Jay Jaeger wrote:
Not necessarily. For example, it is impossible to find an IBM 1410, as
far as I know. But there ARE 1415 consoles I knew of a while back, and
there are certainly 729s and 1403 printers and 1402 card read/punch
units up and running.
There are plenty o
On 07/14/2015 06:10 PM, Jay Jaeger wrote:
Almost sounds like the CPU was kind of an "attached processor" - similar
to the way vector processors have been implemented by IBM and others.
I suppose you could view it that way. There were CPU-less 6000 boxes,
but no PPU-less ones.
--Chuck
On 07/14/2015 07:44 PM, William Donzelli wrote:
IIRC, the KB11 processors used in the DEC 11/45 and 11/70 (and other
related systems) used five "clocks delayed from each other" (more
commonly known as clock phases).
IBM used this method as well on many of their machines.
On the system 360 CPUs,
On 7/14/2015 7:31 PM, Chuck Guzis wrote:
Seymour Cray should have used kinetic sculptures on his machines as part
of eye candy, I guess. Or maybe more chrome...
You got a nice love seat. I could see a early cray style maching in a FPGA
but what good is number crunching if you don't have the me
Meh. You take your machines and I'll take mine. :) The IBM 1410 is a
machine I know well, so I know how it is supposed to work, and I have
detailed information in the form of the ALD's and the CE training
materials to go with it, plus software including diagnostics and
operational software I can
On 7/14/2015 11:16 AM, ben wrote:
>
> Here is the link you have been waiting for, IBM 1130 in FPGA and in the
> FLESH.
> http://ibm1130.blogspot.ca/
>
> Ben.
Thanks for that link. It looks very interesting after a quick glance. I
am sure that I will run into many of the same issues with the SMS
> I suppose you could view it that way. There were CPU-less 6000 boxes, but
> no PPU-less ones.
Were the CPU-less 6000 boxes at least connected to "normal" 6000s with
CPUs using shared ECS, or could they really be completely independent
units using their own ECS?
--
Will
On 2015-07-15 03:13, Noel Chiappa wrote:
> From: Johnny Billquist
> While the pages are variable in length, each page starts at an 8K
> virtual address boundary.
Which is another difference between PDP-11 'pages', and real pages as used on
every other machine of the period which
On 7/14/2015 7:36 PM, Jon Elson wrote:
On 07/14/2015 07:44 PM, William Donzelli wrote:
IIRC, the KB11 processors used in the DEC 11/45 and 11/70 (and other
related systems) used five "clocks delayed from each other" (more
commonly known as clock phases).
IBM used this method as well on many of
Ouch.. thanks for the update.
I sent him an email asking for a price on essentially all of the Commodore
stuff, less the monitor and floppy drives (have plenty of both, and too
heavy to pay for ship).
He said that he wouldn't split up the lots.. which is a little odd, as
everything else in the lo
On 07/14/2015 06:55 PM, Jay Jaeger wrote:
Architecturally, it was pretty much the last of its kind: the last of
the BCD decimal arithmetic machines, which also makes it interesting.
It has also become much more obscure than the 1401, which it followed,
because not nearly as many were made and so
On 07/14/2015 09:42 PM, ben wrote:
I guessing ( no schematic handy) that they made the 360
register file
easy to decode and build with latches.
Not just the register file, but the entire machine. So, all
the hidden registers in the RTL description,
such as storage address register, stor
On 07/14/2015 07:11 PM, William Donzelli wrote:
I suppose you could view it that way. There were CPU-less 6000 boxes, but
no PPU-less ones.
Were the CPU-less 6000 boxes at least connected to "normal" 6000s with
CPUs using shared ECS, or could they really be completely independent
units using t
>Johnny Billquist wrote:
>On 2015-07-14 19:52, Noel Chiappa wrote:
> On Jul 13, 2015, at 8:52 PM, Johnny Billquist update.uu.se> wrote:
> ??? What segments??? The PDP-11 have a plain simple page
table. No
> segments anywhere in sight. And each page is 8K.
I know the processo
Yes, the S/360 had packed decimal - but much more limited in length, and
no wordmark concept.
The 7070 and 7080 were contemporary with the 1410, not after it. They
did not follow it. While data representations were somewhat similar,
the instruction formats were very different.
he 7080 (which ap
The 8086 had four segment registers:
CS - Code segment, used with IP register
DS - Data segment
SS - Stack segment, used with SP and BP registers
ES - Extra segment, used with DI for string instructions as
destination (DS:SI as
On 7/14/15 9:22 PM, Fred Cisin wrote:
The 8086 had four segment registers:
CS- Code segment, used with IP register
DS- Data segment
SS- Stack segment, used with SP and BP registers
ES- Extra segment, used with DI for string instructions as
destination
The 8086 had four segment registers:
CS- Code segment, used with IP register
DS- Data segment
SS- Stack segment, used with SP and BP registers
ES- Extra segment, used with DI for string instructions as
destination (DS:SI as source)
You could override ins
Hi Guys,
I have finally decided to restore my original Altair 8800 which has been in
storage for over 30 years. Does anyone have a copy of Microsoft's Multiuser
Disk Extended Basic for the Altair 8800? When I was in college in '79 to
'81, in the computer room was an ASR-33 Teletype and 3 Learsei
On 7/14/2015 10:22 PM, Fred Cisin wrote:
The 8086 had four segment registers:
CS- Code segment, used with IP register
DS- Data segment
SS- Stack segment, used with SP and BP registers
ES- Extra segment, used with DI for string instructions as
destination
On Wed, 15 Jul 2015, Kip Koon wrote:
Hi Guys,
I have finally decided to restore my original Altair 8800 which has been in
storage for over 30 years. Does anyone have a copy of Microsoft's Multiuser
Disk Extended Basic for the Altair 8800? When I was in college in '79 to
'81, in the computer roo
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