> On Jul 13, 2015, at 8:35 AM, Jay Jaeger <cu...@charter.net> wrote:
>
> Another alternative would be to build a machine up from a Field
> Programmable Gate Array (e.g., the Digilent Nexys2 FPGA development
> board). I recently completed an effort doing that for a 12 bit machine
> we designed and built in a logic/computer design class from racks of
> logic interconnected using IBM unit record plug boards in 1972.
>
> I am going to attempt to do the same for IBM's 1410 computer - a really
> big effort.
That’s been done for all sorts of machines, of course; the PDP-11 comes to mind.
One question would be what design approach you’re using. A behavioral model is
one option; that’s roughly SIMH in an FPGA. And just like SIMH, the model is
only as accurate as your knowledge of the obscure details of the original
design. Depending on the quality of available manuals, this accuracy may be
rather low. (For example, building a PDP-11 model if all you have is a
Processor Handbook may not be accurate enough.)
A different approach is to reproduce the actual logic design. FPGAs can be fed
gate level models, though that’s not the most common practice as I understand
it. But if you have access to that level of original design data, the result
can be quite accurate.
I’ve done a partial gate level model of the CDC 6600, working from the wiring
lists and module schematics. It accurately reproduces (and explains) quite
obscure properties of the peripheral processors, things that aren’t documented
anywhere I know of other than in programmer lore. It also yields a large model
that simulates very slowly...
paul
