> On Jul 14, 2015, at 12:23 PM, ben <bfranc...@jetnet.ab.ca> wrote: > > On 7/13/2015 10:02 AM, Paul Koning wrote: > >> A different approach is to reproduce the actual logic design. FPGAs >> can be fed gate level models, though that’s not the most common >> practice as I understand it. But if you have access to that level >> of original design data, the result can be quite accurate. >> > > The big assumption here, is the software will NOT change the logic model > and the details are vender specific. Altera software is BAD for doing this.
So now I know two reasons not to use AHDL. :-) Yes, it does require that the synthesis software doesn’t have major bugs. And of course, the model has to be sufficiently constrained that it steers the synthesis correctly. In my case, I haven’t reached that point yet. My models currently only run in simulation (GHDL to be specific). paul