On 7/13/2015 10:02 AM, Paul Koning wrote:
A different approach is to reproduce the actual logic design. FPGAs can be fed gate level models, though that’s not the most common practice as I understand it. But if you have access to that level of original design data, the result can be quite accurate.
The big assumption here, is the software will NOT change the logic model and the details are vender specific. Altera software is BAD for doing this. Ben.
