[Mesa-dev] [PATCH 3/3] i965: Stop aux data compare preventing program binary re-use

never will). The only thing the items would be sharing is the instruction data and hence we should only check for that to match and nothing else. No piglit regression in jenkins. CC: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state_cache.c | 52

[Mesa-dev] [PATCH 2/3] i965: Only write program to cache when it doesn't exist yet

Current logic re-writes the same data when existing data is found. Not that this actually matters at the moment in practice, the contraint for finding matching data is too severe to ever allow data to be shared between two items in the cache. CC: Kenneth Graunke Signed-off-by: Topi Pohjolainen

[Mesa-dev] [PATCH 1/3] i965: Rename brw_upload_item_data to brw_alloc_item_data

and simplify the interface to take directly the size and to return the offset. The routine does nothing more than allocate, it doesn't upload anything. CC: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state_cache.c | 19 ++- 1 file ch

[Mesa-dev] [PATCH] gl-2.0: Add test for re-using shader objects

Graunke Signed-off-by: Topi Pohjolainen --- tests/spec/gl-2.0/CMakeLists.gl.txt | 1 + tests/spec/gl-2.0/reuse_fragment_shader.c | 105 ++ 2 files changed, 106 insertions(+) create mode 100644 tests/spec/gl-2.0/reuse_fragment_shader.c diff --git a/tests/spec/gl

[Mesa-dev] [PATCH 05/10] i965: Move tex miptree and format resolving into dispatcher

All hardware platforms have this in common, so do it in the hardware independent dispatcher. v2 (Matt): Removed extra whitespace. v3: Non-trivial rebase Reviewed-by: Matt Turner (v1) Reviewed-by: Kenneth Graunke (v1) Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h

[Mesa-dev] [PATCH 02/10] i965: Reduce the scope of input in buffer tex setup

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 4 ++-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 +++- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 +- src/mesa/drivers/dri/i965/gen8_surface_state.c| 2 +- 4 files changed, 7

[Mesa-dev] [PATCH 10/10] i965: Remove update_texture_surface()

This is not needed anymore. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 7 -- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 29 --- src/mesa/drivers/dri/i965/gen8_surface_state.c| 26 3 files

[Mesa-dev] [PATCH 09/10] i965: Use emit_texture_surface_state() directly

account. Normally this isn't needed for gen < 7 as those do not support GL_ARB_texture_view. However, our meta path for 2D blits requires it regardless if the extension is officially supported. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surf

[Mesa-dev] [PATCH 07/10] i965: Move texture swizzle resolving into dispatcher

v2: Non-trivial rebase Reviewed-by: Matt Turner (v1) Reviewed-by: Kenneth Graunke (v1) Signed-off-by: Topi Pohjolainen Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 14 -- src

[Mesa-dev] [PATCH 08/10] i965: Refactor effective depth calculation

v2: Non-trivial rebase Reviewed-by: Matt Turner (v1) Reviewed-by: Kenneth Graunke (v1) Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 9 - src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 04/10] i965/gen4: Use tex object format instead of the miptree format

Equivalent logic for newer generations (>= 7) use the tex object format instead. This patch prepares for merging the decision making for all generations. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +- 1 file changed, 1 insertion(+), 1 delet

[Mesa-dev] i965: Yet another revision of tex surface setup refactoring

weight launch mechanism for meta blits and clears. CC: Matt Turner CC: Kenneth Graunke CC: Francisco Jerez Topi Pohjolainen (10): i965: Use constant miptree pointer in tex surface setup i965: Reduce the scope of input in buffer tex setup i965: Move tex buffer dispatch into hw independent

[Mesa-dev] [PATCH 03/10] i965: Move tex buffer dispatch into hw independent setup

(v1) Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 28 ++-- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index

[Mesa-dev] [PATCH 01/10] i965: Use constant miptree pointer in tex surface setup

as it is only used for reading. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 +- src/mesa/drivers/dri/i965/gen8_surface_state.c| 2 +- 3 files changed, 3 insertions(+), 3 deletions

[Mesa-dev] [PATCH 06/10] i965/gen7: Move tex gather format override into common dispatcher

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index c14f00a..b68b136 100644 --- a/src/mesa/drivers

[Mesa-dev] [PATCH] i965/wm/gen7: Refactor state setup

v2: Rebased to include consideration for atomic ops in the shader. CC: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 9 +++ src/mesa/drivers/dri/i965/gen7_wm_state.c | 102 +++--- 2 files changed, 75 insertions

[Mesa-dev] meta/blit: Write gl_FragDepth only when really needed

in the shader. While this didn't improve any performance benches I tried, it doesn't seem to introduce any regressions either in the benches or with piglit. Topi Pohjolainen (5): meta/blit: Add plumbing for shaders without depth meta/blit: Write depth only when asked for meta/bli

[Mesa-dev] [PATCH 3/5] meta/blit: Compile programs with and without depth

or improvements. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/common/meta.h | 3 ++- src/mesa/drivers/common/meta_blit.c | 13 + 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/common/meta.h b/src/mesa/drivers/common/meta.h index de3dc6a

[Mesa-dev] [PATCH 5/5] meta: Don't write depth when decompressing tex-images

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/common/meta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c index 45035b1..6ddec73 100644 --- a/src/mesa/drivers/common/meta.c +++ b/src/mesa/drivers/common

[Mesa-dev] [PATCH 4/5] meta: Don't write depth when generating miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/common/meta_generate_mipmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/common/meta_generate_mipmap.c b/src/mesa/drivers/common/meta_generate_mipmap.c index c38b46b..c1b6d3c 100644 --- a/src/mesa

[Mesa-dev] [PATCH 2/5] meta/blit: Write depth only when asked for

g6<8,8,1>F sampler (1, 0, 0, 1) mlen 2 rlen 4{ align1 1Q }; sendc(8) nullg124<8,8,1>F render RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT }; Signed-off-by: Topi Pohjolainen CC: Kenneth Graunke --- src/mesa/drivers/common/meta.c | 7 --

[Mesa-dev] [PATCH 1/5] meta/blit: Add plumbing for shaders without depth

Currently all blit programs are unconditionally compiled with gl_FragDepth. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/common/meta.c | 3 ++- src/mesa/drivers/common/meta.h | 1 + src/mesa/drivers/common/meta_blit.c| 2 +- src/mesa/drivers

[Mesa-dev] [PATCH 05/17] glsl/ir: Add printing support for doubles (was: add double support)

From: Dave Airlie Signed-off-by: Dave Airlie --- src/glsl/ir_print_visitor.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/glsl/ir_print_visitor.cpp b/src/glsl/ir_print_visitor.cpp index bd39805..3600827 100644 --- a/src/glsl/ir_print_visitor.cpp +++ b/src/glsl/ir_print

[Mesa-dev] [PATCH 08/17] glsl/ir: Add builder support for functions with double floats

From: Dave Airlie (was: add double support) Signed-off-by: Dave Airlie --- src/glsl/ir_builder.cpp | 23 +++ src/glsl/ir_builder.h | 5 + 2 files changed, 28 insertions(+) diff --git a/src/glsl/ir_builder.cpp b/src/glsl/ir_builder.cpp index a2f6f29..37bbffa 100644 -

[Mesa-dev] [PATCH 04/17] glsl/ir: Add builtin function support for doubles (was: add double support)

From: Dave Airlie Signed-off-by: Dave Airlie --- src/glsl/ir.cpp | 104 ++-- src/glsl/ir.h | 21 src/glsl/ir_validate.cpp| 61 --- src/mesa/program/ir_to_mesa.cpp | 10 4 files cha

[Mesa-dev] [PATCH 03/17] glsl: Uniform linking support for doubles (was: add double support)

From: Dave Airlie Signed-off-by: Dave Airlie --- src/glsl/link_uniforms.cpp | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/glsl/link_uniforms.cpp b/src/glsl/link_uniforms.cpp index de2f6c9..0db70d5 100644 --- a/src/glsl/link_uniforms.cpp +++ b/src/glsl/link_unifo

[Mesa-dev] [PATCH 06/17] glsl/ir: Add cloning support for doubles (was: add double support)

From: Dave Airlie Signed-off-by: Dave Airlie --- src/glsl/ir_clone.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/ir_clone.cpp b/src/glsl/ir_clone.cpp index dffa578..5c7279c 100644 --- a/src/glsl/ir_clone.cpp +++ b/src/glsl/ir_clone.cpp @@ -327,6 +327,7 @@ ir_constant::clone(v

[Mesa-dev] [PATCH 07/17] glsl/ir: Add builtin constant function support for doubles

From: Dave Airlie (was: add double support) Signed-off-by: Dave Airlie --- src/glsl/ir_constant_expression.cpp | 234 +++- 1 file changed, 202 insertions(+), 32 deletions(-) diff --git a/src/glsl/ir_constant_expression.cpp b/src/glsl/ir_constant_expression.cpp

[Mesa-dev] Split version of 07/13 glsl: add double support

I wanted to try if this could be split into smaller chunks to aid review. Only compile tested (each step compiles). Dave Airlie (17): glsl: Add double builtin type (was: add double support) glsl: Add double builtin type generation (was: add double support) glsl: Uniform linking support for d

[Mesa-dev] [PATCH 09/17] glsl: Add support doubles in optimization passes (was: add double support)

From: Dave Airlie Signed-off-by: Dave Airlie --- src/glsl/opt_constant_propagation.cpp | 3 +++ src/glsl/opt_minmax.cpp | 13 + 2 files changed, 16 insertions(+) diff --git a/src/glsl/opt_constant_propagation.cpp b/src/glsl/opt_constant_propagation.cpp index c334e12

[Mesa-dev] [PATCH 01/17] glsl: Add double builtin type (was: add double support)

From: Dave Airlie Signed-off-by: Dave Airlie --- src/glsl/builtin_type_macros.h | 16 ++ src/glsl/glsl_parser_extras.h | 5 ++ src/glsl/glsl_types.cpp| 109 + src/glsl/glsl_types.h | 18 ++- 4 files changed, 125 insertions(+)

[Mesa-dev] [PATCH 10/17] glsl: Add ubo lowering support for doubles (was: add double support)

From: Dave Airlie Signed-off-by: Dave Airlie --- src/glsl/lower_ubo_reference.cpp | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/glsl/lower_ubo_reference.cpp b/src/glsl/lower_ubo_reference.cpp index 43dd067..e539491 100644 --- a/src/glsl/lower_ubo_referen

[Mesa-dev] [PATCH 02/17] glsl: Add double builtin type generation (was: add double support)

From: Dave Airlie Perhaps squash this with previous. Signed-off-by: Dave Airlie --- src/glsl/builtin_types.cpp | 30 ++ 1 file changed, 30 insertions(+) diff --git a/src/glsl/builtin_types.cpp b/src/glsl/builtin_types.cpp index 10fac0f..fef86df 100644 --- a/src/gls

[Mesa-dev] [PATCH 12/17] glsl/parser: Support double floats (was: add double support)

From: Dave Airlie Signed-off-by: Dave Airlie --- src/glsl/glsl_parser.yy | 33 + 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy index 7fb8c38..596e432 100644 --- a/src/glsl/glsl_parser.yy +++ b/src

[Mesa-dev] [PATCH 16/17] glsl: Linking support for doubles (was: add double support)

From: Dave Airlie Signed-off-by: Dave Airlie --- src/glsl/link_uniform_initializers.cpp | 7 ++- src/glsl/link_varyings.cpp | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/glsl/link_uniform_initializers.cpp b/src/glsl/link_uniform_initializers.cpp in

[Mesa-dev] [PATCH 11/17] glsl/ast: Support double floats (was: add double support)

From: Dave Airlie Signed-off-by: Dave Airlie --- src/glsl/ast.h | 2 ++ src/glsl/ast_function.cpp | 67 + src/glsl/ast_to_hir.cpp | 38 +-- src/glsl/glsl_parser_extras.cpp | 4 +++ 4 files changed, 96 i

[Mesa-dev] [PATCH 13/17] glsl/lexer: Support double floats (was: add double support)

From: Dave Airlie Signed-off-by: Dave Airlie --- src/glsl/glsl_lexer.ll | 42 ++ 1 file changed, 38 insertions(+), 4 deletions(-) diff --git a/src/glsl/glsl_lexer.ll b/src/glsl/glsl_lexer.ll index 57c46be..de58e73 100644 --- a/src/glsl/glsl_lexer.ll +++

[Mesa-dev] [PATCH 15/17] glsl: Support double loop control (was: add double support)

From: Dave Airlie Signed-off-by: Dave Airlie --- src/glsl/loop_controls.cpp | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/src/glsl/loop_controls.cpp b/src/glsl/loop_controls.cpp index 1c1d34f..9a99c21 100644 --- a/src/glsl/loop_controls.cpp +++ b/src/g

[Mesa-dev] [PATCH 17/17] glsl: add double support

From: Dave Airlie This adds the guts of the fp64 implementation to the GLSL compiler. - builtin double types - double constant support - lexer parsing for double types (lf, LF) - enforcing flat on double fs inputs - double operations (d2f,f2d, pack/unpack, frexp - in 2 parts) - ir builder bits.

[Mesa-dev] [PATCH 14/17] glsl: Support double inouts (was: add double support)

From: Dave Airlie Signed-off-by: Dave Airlie --- src/glsl/ir_set_program_inouts.cpp | 24 +--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/src/glsl/ir_set_program_inouts.cpp b/src/glsl/ir_set_program_inouts.cpp index 97ead75..4aa402e 100644 --- a/src/glsl

[Mesa-dev] [RFC] i965: Factor out descriptor building for indirect send messages

c and wanted to try to something else. I believe patch number five should go nicely on top of this as the descriptor instruction could be followed by (or preceeeded by) any additional instructions modifying the descriptor register before the actual send instruction. Signed-off-by: Topi Pohjol

[Mesa-dev] [v2 6/9] i965: Add support for tex upload using gpu

, it is handled by _mesa_image_offset() automatically (Ken). - Support 1D_ARRAY by flipping depth, width and y, z (Ken). CC: Kenneth Graunke CC: Anuj Phogat Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_tex.h | 8 ++ src/mesa/drivers/dri/i965

[Mesa-dev] [v2 4/9] i965: Estimate batch space per shader stage

sible with blorp tex uploads (HSW with piglit test max-samplers). One runs out of space while batch wrapping isn't allowed. v2: Rebase on top of current upstream Signed-off-by: Topi Pohjolainen CC: Kenneth Graunke CC: Jason Ekstrand --- src/mesa/drivers/dri/i965/

[Mesa-dev] [PATCH 01/16] i965/miptree: Tell if anything got resolved

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 ++-- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 02/16] i965/gen6+: Implement end-of-pipe sync

Implementation for gen < 6 is taken as copy-paste from brw_emit_mi_flush() in order to preserve the behavior in later patches. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_pipe_control.c |

[Mesa-dev] [PATCH 04/16] i965: Hook end-of-pipe-sync after image resolves

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 80 +++-- 1 file changed, 47 insertions(+), 33 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 9ca1ac1..f4ebaf2 100644

[Mesa-dev] i965: On-demand render target flushing

that one needs to be rather careful with it - performance gets decreased noticeably when used unneeded. I don't really know if we want to go this way myself even. Current logic - while not ideal - is rather simple. Topi Pohjolainen (16): i965/miptree: Tell if anything got resolved i965/gen

[Mesa-dev] [PATCH 03/16] i965: Hook end-of-pipe-sync after texture resolves

without the driver necessarily knowing. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 113 1 file changed, 99 insertions(+), 14 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 06/16] i965: Consider layered rt resolves along with other

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 15 +++ src/mesa/drivers/dri/i965/brw_draw.c| 34 - 2 files changed, 15 insertions(+), 34 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa

[Mesa-dev] [PATCH 07/16] i965: Add color resolve end-of-pipe-sync before switch to blit ring

This ensures that all rendering is finished and gpu caches are flushed out. These are paths trying to switch to blit engine. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_blit.c | 16 src/mesa/drivers/dri/i965/intel_copy_image.c | 10

[Mesa-dev] [PATCH 05/16] i965: Hook end-of-pipe-sync after framebuffer resolves

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 101 1 file changed, 51 insertions(+), 50 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index f4ebaf2..746d754 100644

[Mesa-dev] [PATCH 10/16] i965: Add end-of-pipe sync before non-gpu read of color resolves

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 src/mesa/drivers/dri/i965/intel_tex_image.c| 10 -- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 11 +-- 3 files changed, 21 insertions(+), 8 deletions(-) diff --git a/src

[Mesa-dev] [PATCH 13/16] i965/blorp: Use conditional end-of-pipe-sync

instead of unconditional render cache flush. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 23 --- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c

[Mesa-dev] [PATCH 09/16] i965/miptree: Add color resolve end-of-pipe-sync before sharing

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 717a320..b0148d2 100644 --- a/src

[Mesa-dev] [PATCH 08/16] i965/dri2: Add end-of-pipe-sync after color resolves

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index bb84102..75d4920 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 14/16] i965: Consider surface resolves and sync after blorp ops

ble on gen < 6. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_compute.c | 2 ++ src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_draw.c | 2 ++ src/mesa/drivers/dr

[Mesa-dev] [PATCH 15/16] i965: Check if fast color clear state transition needs sync

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 49 + 1 file changed, 49 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 52f8c17..28ed8d1 100644 --- a/src/mesa

[Mesa-dev] [PATCH 12/16] i965/blorp/blit: Refactor hiz/ccs prep for blits

They are explicitly considered for blits from now on. Currently they are part of common surface preparation which is used by all blorp ops. However, color/hiz/depth/stencil clears and resolves use hiz/ccs without the tweaks. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 16/16] i965/blorp: Drop unnecessary flushes after clear/resolve

Now that there is proper end-of-pipe synchronization the additional delay needed before has become redundant. On SKL helps: OglDrvRes: 1.65304% +/- 0.0816077% by making blorp blits/copies more competitive. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 39

[Mesa-dev] [PATCH 11/16] i965/blorp: Do more fine grained flushing/syncing

texture uploads which require excess flushing to be omitted in order to perform properly. Now that clears and blits make the decision independently that also becomes easier. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 48 + src/mesa

[Mesa-dev] [RFC] i965: Restructure CCS disable

From: Ben Widawsky Make the code only disable CCS when it has to, unlike before where it disabled CCS and enabled it when it could. This is much more inline with how it should work in a few patches, where we have fewer restrictions as to when we disable CCS. v2: Change CCS disabling to an assert

[Mesa-dev] [v2 22/27] intel/isl: Apply render target alignment constraints for MCS

v2: Instead of having the same block in isl_gen7,8,9.c add it once into isl.c::isl_choose_image_alignment_el() instead. CC: Jason Ekstrand Signed-off-by: Topi Pohjolainen --- src/intel/isl/isl.c | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/intel

[Mesa-dev] [v2 17/27] i965/gen6/hiz: Add direct buffer size resolver

ead of _mesa_is_cube_map_texture(mt->target)). Reviewed-by: Jason Ekstrand (v1) Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_tex_layout.c| 37 +++ src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 23 +++-- src/mesa/drivers/dr

[Mesa-dev] [0.5/16] i965/blorp/gen9: Do not try deferred mcs allocation for CCS_E

. Currently the deferred hook is also applied for gen9 and blorp clears therefore effectively revert the heuristic. This also prevents blorp from wrongly falling to meta path when the deferred mcs allocation fails for x-tiled miptrees. CC: Jason Ekstrand CC: Ben Widawsky Signed-off-by: Topi

[Mesa-dev] [v2 6/9] i965: Add support for tex upload using gpu

Graunke CC: Anuj Phogat Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_tex.h | 8 ++ src/mesa/drivers/dri/i965/intel_tex_subimage.c | 191 + 2 files changed, 199 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_tex.h b/src/mesa

[Mesa-dev] [v2 7/9] i965/blorp: Use for tex_image_2d

s sampling rounds. OglDrvShComp:1.59058% +/- 0.239194% OglMultithread: 3.07351% +/- 0.283737% Signed-off-by: Topi Pohjolainen CC: Jason Ekstrand --- src/mesa/drivers/dri/i965/intel_tex_image.c | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_tex_imag

[Mesa-dev] [v2 8/9] i965/blorp: Use for tex_subimage_2d

OglTerrainFlyInst: 4.3506% +/- 0.359936% (N = 14) OglTerrainFlyTess: 3.5859% +/- 0.221177% (N = 15) Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [v2 4/9] i965: Estimate batch space per shader stage

sible with blorp tex uploads (HSW with piglit test max-samplers). One runs out of space while batch wrapping isn't allowed. v2: Rebase on top of current upstream v3: Take binding table alignment into account (Jason) Signed-off-by: Topi Pohjolainen CC: Kenneth Graunke CC: Jason Ekstrand

[Mesa-dev] [PATCH 05/26] i965: Set fast clear state only once in render cycle

Blorp operations used to set it before rendering and again just after. Calling intel_miptree_used_for_rendering() for gen6 and earlier as well as for hiz is a no-op. It only deals with color buffers supporting fast clear/lossless compression. Signed-off-by: Topi Pohjolainen --- src/mesa

[Mesa-dev] [PATCH 08/26] i965: Provide slice details to color resolver

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 14 -- src/mesa/drivers/dri/i965/brw_blorp.h | 3 ++- src/mesa/drivers/dri/i965/brw_context.c | 16 +++- src/mesa/drivers/dri/i965/intel_blit.c| 8 ++-- src

[Mesa-dev] [PATCH 02/26] i965: Add multi-slice getter for resolve maps

This is useful when checking if any slice is in unresolved state. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_resolve_map.c | 13 - src/mesa/drivers/dri/i965/intel_resolve_map.h | 21 +++-- 2 files changed, 27 insertions(+), 7 deletions

[Mesa-dev] i965: Fast color clear for mipmapped and arrayed

patch overallocates in some cases but should be safe though. I will follow-up with some performance numbers. Ben Widawsky (2): i965: Restructure fast clear eligibility decision i965: Enable fast clears for multi-lod Topi Pohjolainen (24): i965/meta: Split conversion of color and setting it

[Mesa-dev] [PATCH 10/26] i965: Provide slice details to renderbuffer fast clear state tracker

This patch also introduces getter and setter for fast clear state preparing for tracking the state per slice. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 7 ++-- src/mesa/drivers/dri/i965/brw_draw.c | 12 --- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 07/26] i965: Expose physical to logical layer converter

Fast color clear state will be tracked in terms logical layers. Miptrees in turn work internally in terms of physical layers. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 37 --- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 14

[Mesa-dev] [PATCH 03/26] intel/blorp: Add plumbing for color resolve slice details

Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp.h | 3 ++- src/intel/blorp/blorp_clear.c | 9 +++-- src/mesa/drivers/dri/i965/brw_blorp.c | 2 +- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h

[Mesa-dev] [PATCH 16/26] i965: Set initial msaa fast clear status explicitly

instead of in intel_miptree_init_mcs(). For lossless compression the status is immediately overwritten in intel_miptree_alloc_non_msrt_mcs() while the status for non-compressed non-msaa miptrees is explicitly set in do_blorp_clear(). Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 04/26] i965/fbo: Prepare layer multiplier for render buffer compression

This path is not yet taken for fast cleared or compressed buffers but later patches will enable it. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_fbo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa

[Mesa-dev] [PATCH 06/26] i965: Add new interface for full color resolves

Upcoming patches will introduce fast clear in level/layer granularity like the driver does already for depth/hiz. This patch introduces equivalent full resolve option. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c| 6 +++--- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 01/26] i965/meta: Split conversion of color and setting it

And fix a mangled comment while at it. Signed-off-by: Topi Pohjolainen CC: Ben Widawsky CC: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_blorp.c | 7 +++- src/mesa/drivers/dri/i965/brw_meta_util.c | 56 +-- src/mesa/drivers/dri/i965/brw_meta_util.h | 10

[Mesa-dev] [PATCH 17/26] i965: Track fast color clear state in level/layer granularity

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 63 +++ src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 14 +++--- 2 files changed, 52 insertions(+), 25 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src

[Mesa-dev] [PATCH 13/26] i965: Refactor check if color resolve is needed

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 43 +-- 1 file changed, 27 insertions(+), 16 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index ee63477

[Mesa-dev] [PATCH 15/26] i965: Declare read-only input to level/layer check const

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 2ef2d20..8c53fa0 100644 --- a/src/mesa

[Mesa-dev] [PATCH 19/26] i965/gen9: Do not use fast clear on compressed mipmapped/arrayed

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 12 1 file changed, 12 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 8782424..d937c5c 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c

[Mesa-dev] [PATCH 18/26] i965: Track fast clear color in level/layer granularity

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c| 29 --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 28 --- src/mesa/drivers/dri/i965/intel_mipmap_tree.h| 45

[Mesa-dev] [PATCH 14/26] i965: Move fast clear state enumeration into resolve map

Status is still tracked per miptree. Next patch will switch to resolve map per slice/level. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 58 -- src/mesa/drivers/dri/i965/intel_resolve_map.c | 6 +-- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 09/26] i965: Split per miptree and per slice/level fast clear bits

own boolean. Possible follow-up work is to combine disable_aux_buffers and no_msrt_mcs into single enum. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 2 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 +- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 26/26] i965: Enable fast clears for multi-lod

From: Ben Widawsky Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 932220e..5769bee 100644

[Mesa-dev] [PATCH 20/26] i965: Resolve non-compressed fast clears prior layered rendering

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_draw.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index e387eb9..df342d7 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c

[Mesa-dev] [PATCH 25/26] i965/gen8: Relax asserts prohibiting arrayed/mipmapped fast clears

Signed-off-by: Topi Pohjolainen --- src/intel/isl/isl.c | 3 +-- src/mesa/drivers/dri/i965/brw_blorp.c | 6 +++--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 23 +-- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++- 4 files

[Mesa-dev] [PATCH 11/26] i965: Add interface for checking multiple slices if any is unresolved

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 + 2 files changed, 13 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [PATCH 23/26] i965: Restructure fast clear eligibility decision

From: Ben Widawsky Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 51 ++- 1 file changed, 34 insertions(+), 17 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index

[Mesa-dev] [PATCH 22/26] i965: Add non-msrt mcs array/mipmap alignment restrictions

mip-levels and the latter for qpitch. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 68 +++- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 31 ++- src/mesa/driver

[Mesa-dev] [PATCH 21/26] i965: Merge qpitch return paths

Upcoming patches need to consider if additional alignment is needed for arrayed/mipmapped and single-sampled mcs buffer. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/mesa

[Mesa-dev] [PATCH 24/26] i965: Disable aux buffers with non-compatible copies

Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp.h | 2 ++ src/intel/blorp/blorp_blit.c | 6 ++ src/mesa/drivers/dri/i965/brw_blorp.c | 25 - 3 files changed, 28 insertions(+), 5 deletions(-) diff --git a/src/intel/blorp/blorp.h b

[Mesa-dev] [PATCH 12/26] i965: Add plumbing for fast clear layer/level details

on when the actual functionality is enabled. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c| 32 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 34 2 files changed, 42 insertions(+), 24 deletions(-) diff

[Mesa-dev] [PATCH 01/12] i965/rbc: Allow integer formats as advertised in isl_format.c

e the lossless compression being effectively turned off for integer formats. Once the mcs buffer is allocated beforehand, the assertion addressed here would start triggering. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 6 +- 1 file changed, 5 insertions(+), 1 del

[Mesa-dev] [PATCH 03/12] isl/gen8+: Allow 3D auxiliary surfaces

Otherwise once mcs buffer gets allocated without delay for lossless compression (same as we do for msaa), assert starts to fire in piglit case: tex3d. The test uses depth of one which is in fact supported even now. Signed-off-by: Topi Pohjolainen --- src/intel/isl/isl.c | 7 ++- 1 file

[Mesa-dev] i965: Hardware assisted layered clears

Jason Ekstrand Topi Pohjolainen (12): i965/rbc: Allow integer formats as advertised in isl_format.c i965/rbc: Set aux surface unconditionally for sampling engine isl/gen8+: Allow 3D auxiliary surfaces i965/rbc: Allocate mcs directly i965/blorp: Skip redundant re-fast clear for non-compressed

[Mesa-dev] [PATCH 10/12] intel/blorp: Add plumbing for setting color clear layer count

Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp.h | 6 +++--- src/intel/blorp/blorp_clear.c | 16 +--- src/mesa/drivers/dri/i965/brw_blorp.c | 6 +++--- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/src/intel/blorp/blorp.h b/src

[Mesa-dev] [PATCH 05/12] i965/blorp: Skip redundant re-fast clear for non-compressed

Originally re-clears where skipped but when lossless compression was introduced the re-clears where errorneously enabled also for non-compressed fast clears. Signed-off-by: Topi Pohjolainen CC: Ben Widawsky CC: Kenneth Graunke CC: Harri Syrja Cc: Chad Versace --- src/mesa/drivers/dri/i965

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