Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_context.c | 15 +++++++++++++++
src/mesa/drivers/dri/i965/brw_draw.c | 34 ---------------------------------
2 files changed, 15 insertions(+), 34 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 746d754..bb84102 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -366,6 +366,21 @@ brw_prepare_framebuffer(struct gl_context *ctx)
if (intel_miptree_all_slices_resolve_color(brw, irb->mt, 0))
flush |= INTEL_WRITE_CACHE_SYNC;
}
+
+ /* For layered rendering non-compressed fast cleared buffers need to be
+ * resolved. Surface state can carry only one fast color clear value
+ * while each layer may have its own fast clear color value. For
+ * compressed buffers color value is available in the color buffer.
+ */
+ if (irb->layer_count > 1 &&
+ !(irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS) &&
+ !intel_miptree_is_lossless_compressed(brw, irb->mt)) {
+ assert(brw->gen >= 8);
+
+ if (intel_miptree_resolve_color(brw, irb->mt, irb->mt_level,
+ irb->mt_layer, irb->layer_count, 0))
+ flush |= INTEL_WRITE_CACHE_SYNC;
+ }
}
return flush;
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 940ce70..564739c 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -395,39 +395,6 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw)
}
}
-static void
-brw_predraw_set_aux_buffers(struct brw_context *brw)
-{
- if (brw->gen < 9)
- return;
-
- struct gl_context *ctx = &brw->ctx;
- struct gl_framebuffer *fb = ctx->DrawBuffer;
-
- for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
- struct intel_renderbuffer *irb =
- intel_renderbuffer(fb->_ColorDrawBuffers[i]);
-
- if (!irb) {
- continue;
- }
-
- /* For layered rendering non-compressed fast cleared buffers need to be
- * resolved. Surface state can carry only one fast color clear value
- * while each layer may have its own fast clear color value. For
- * compressed buffers color value is available in the color buffer.
- */
- if (irb->layer_count > 1 &&
- !(irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS) &&
- !intel_miptree_is_lossless_compressed(brw, irb->mt)) {
- assert(brw->gen >= 8);
-
- intel_miptree_resolve_color(brw, irb->mt, irb->mt_level,
- irb->mt_layer, irb->layer_count, 0);
- }
- }
-}
-
/* May fail if out of video memory for texture or vbo upload, or on
* fallback conditions.
*/
@@ -476,7 +443,6 @@ brw_try_draw_prims(struct gl_context *ctx,
util_last_bit(ctx->VertexProgram._Current->SamplersUsed);
intel_prepare_render(brw);
- brw_predraw_set_aux_buffers(brw);
/* This workaround has to happen outside of brw_upload_render_state()
* because it may flush the batchbuffer for a blit, affecting the state
--
2.5.5
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