Now that there is proper end-of-pipe synchronization the additional
delay needed before has become redundant. On SKL helps:
OglDrvRes: 1.65304% +/- 0.0816077%
by making blorp blits/copies more competitive.
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 39 +++++++++++++++--------------------
1 file changed, 17 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index bc9f964..3c8a7bd 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -992,18 +992,24 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
x0, y0, x1, y1,
clear_color, color_write_disable);
blorp_batch_finish(&batch);
- }
- /*
- * Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
- *
- * Any transition from any value in {Clear, Render, Resolve} to a
- * different value in {Clear, Render, Resolve} requires end of pipe
- * synchronization.
- */
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_RENDER_TARGET_FLUSH |
- PIPE_CONTROL_CS_STALL);
+ const bool is_x_tiled = irb->mt->tiling == I915_TILING_X;
+ const bool is_compressed_msaa = irb->mt->mcs_buf &&
+ irb->mt->num_samples > 1;
+
+ /* HACK: Workaround unknown bug. This used to be unconditional for
+ * all clears even though originally meant only for fast clears. It
+ * seems it has been hiding bug(s). It looks that it is really
+ * brw_try_draw_prims() that is missing this. But unfortunately there is
+ * no way of detecting non-fast clears with current bookkeeping and
+ * doing this flush unconditionally there hurts performance in many
+ * cases.
+ */
+ if (brw->gen >= 9 && (is_x_tiled || is_compressed_msaa))
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_RENDER_TARGET_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+ }
return true;
}
@@ -1082,17 +1088,6 @@ brw_blorp_resolve_color(struct brw_context *brw, struct
intel_mipmap_tree *mt,
brw_blorp_to_isl_format(brw, format, true),
resolve_op);
blorp_batch_finish(&batch);
-
- /*
- * Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
- *
- * Any transition from any value in {Clear, Render, Resolve} to a
- * different value in {Clear, Render, Resolve} requires end of pipe
- * synchronization.
- */
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_RENDER_TARGET_FLUSH |
- PIPE_CONTROL_CS_STALL);
}
static void
--
2.5.5
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