Blorp operations used to set it before rendering and again just
after.
Calling intel_miptree_used_for_rendering() for gen6 and earlier
as well as for hiz is a no-op. It only deals with color buffers
supporting fast clear/lossless compression.
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 24 ++++--------------------
src/mesa/drivers/dri/i965/brw_draw.c | 5 +----
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 ---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 ++++--
4 files changed, 9 insertions(+), 29 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index ecfcef5..aba2e66 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -371,7 +371,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
intel_miptree_check_level_layer(src_mt, src_level, src_layer);
intel_miptree_check_level_layer(dst_mt, dst_level, dst_layer);
- intel_miptree_used_for_rendering(dst_mt);
+ intel_miptree_used_for_rendering(brw, dst_mt);
struct isl_surf tmp_surfs[4];
struct blorp_surf src_surf, dst_surf;
@@ -402,9 +402,6 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
blorp_batch_finish(&batch);
intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_layer);
-
- if (intel_miptree_is_lossless_compressed(brw, dst_mt))
- dst_mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
}
void
@@ -437,7 +434,7 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
miptree_check_level_logical_layer(src_mt, src_level, src_layer);
miptree_check_level_logical_layer(dst_mt, dst_level, dst_layer);
- intel_miptree_used_for_rendering(dst_mt);
+ intel_miptree_used_for_rendering(brw, dst_mt);
struct isl_surf tmp_surfs[4];
struct blorp_surf src_surf, dst_surf;
@@ -454,9 +451,6 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
blorp_batch_finish(&batch);
intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_layer);
-
- if (intel_miptree_is_lossless_compressed(brw, dst_mt))
- dst_mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
}
static struct intel_mipmap_tree *
@@ -856,8 +850,6 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
}
}
- intel_miptree_used_for_rendering(irb->mt);
-
/* We can't setup the blorp_surf until we've allocated the MCS above */
struct isl_surf isl_tmp[2];
struct blorp_surf surf;
@@ -883,6 +875,8 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
*/
irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
} else {
+ intel_miptree_used_for_rendering(brw, irb->mt);
+
DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__,
irb->mt, irb->mt_level, irb->mt_layer, num_layers);
@@ -898,14 +892,6 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
x0, y0, x1, y1,
clear_color, color_write_disable);
blorp_batch_finish(&batch);
-
- if (is_lossless_compressed) {
- /* Compressed buffers can be cleared also using normal rep-clear. In
- * such case they behave such as if they were drawn using normal 3D
- * render pipeline, and we simply mark the mcs as dirty.
- */
- irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
- }
}
return true;
@@ -954,7 +940,6 @@ brw_blorp_resolve_color(struct brw_context *brw, struct
intel_mipmap_tree *mt)
const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
intel_miptree_check_level_layer(mt, 0 /* level */, 0 /* layer */);
- intel_miptree_used_for_rendering(mt);
struct isl_surf isl_tmp[2];
struct blorp_surf surf;
@@ -975,7 +960,6 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct
intel_mipmap_tree *mt,
unsigned int level, unsigned int layer, enum blorp_hiz_op
op)
{
intel_miptree_check_level_layer(mt, level, layer);
- intel_miptree_used_for_rendering(mt);
assert(intel_miptree_level_has_hiz(mt, level));
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 68add7f..5680403 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -388,10 +388,7 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw)
if (irb) {
brw_render_cache_set_add_bo(brw, irb->mt->bo);
-
- if (intel_miptree_is_lossless_compressed(brw, irb->mt)) {
- irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
- }
+ intel_miptree_used_for_rendering(brw, irb->mt);
}
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c84fd53..5e9a7c1 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -199,7 +199,6 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
}
assert(brw_render_target_supported(brw, rb));
- intel_miptree_used_for_rendering(mt);
mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
@@ -988,8 +987,6 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
}
}
- intel_miptree_used_for_rendering(irb->mt);
-
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset);
format = brw->render_target_format[rb_format];
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 2f1b8eb..a794db4 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -938,13 +938,15 @@ intel_miptree_all_slices_resolve_depth(struct brw_context
*brw,
* for rendering.
*/
static inline void
-intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
+intel_miptree_used_for_rendering(const struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
{
/* If the buffer was previously in fast clear state, change it to
* unresolved state, since it won't be guaranteed to be clear after
* rendering occurs.
*/
- if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
+ if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR ||
+ intel_miptree_is_lossless_compressed(brw, mt))
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
}
--
2.5.5
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