Fast color clear state will be tracked in terms logical layers.
Miptrees in turn work internally in terms of physical layers.
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 37 ++++++++-------------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 14 ++++++++++
2 files changed, 25 insertions(+), 26 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index aba2e66..4030038 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -274,20 +274,6 @@ swizzle_to_scs(GLenum swizzle)
return (enum isl_channel_select)((swizzle + 4) & 7);
}
-static unsigned
-physical_to_logical_layer(struct intel_mipmap_tree *mt,
- unsigned physical_layer)
-{
- if (mt->num_samples > 1 &&
- (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
- mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS)) {
- assert(physical_layer % mt->num_samples == 0);
- return physical_layer / mt->num_samples;
- } else {
- return physical_layer;
- }
-}
-
static void
miptree_check_level_logical_layer(struct intel_mipmap_tree *mt,
unsigned level,
@@ -327,6 +313,11 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
GLenum filter, bool mirror_x, bool mirror_y,
bool decode_srgb, bool encode_srgb)
{
+ const unsigned src_logical_layer =
+ intel_miptree_physical_to_logical_layer(src_mt, src_layer);
+ const unsigned dst_logical_layer =
+ intel_miptree_physical_to_logical_layer(dst_mt, dst_layer);
+
/* Get ready to blit. This includes depth resolving the src and dst
* buffers if necessary. Note: it's not necessary to do a color resolve on
* the destination buffer because we use the standard render path to render
@@ -389,11 +380,9 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw);
- blorp_blit(&batch, &src_surf, src_level,
- physical_to_logical_layer(src_mt, src_layer),
+ blorp_blit(&batch, &src_surf, src_level, src_logical_layer,
brw_blorp_to_isl_format(brw, src_format, false), src_isl_swizzle,
- &dst_surf, dst_level,
- physical_to_logical_layer(dst_mt, dst_layer),
+ &dst_surf, dst_level, dst_logical_layer,
brw_blorp_to_isl_format(brw, dst_format, true),
ISL_SWIZZLE_IDENTITY,
src_x0, src_y0, src_x1, src_y1,
@@ -756,12 +745,6 @@ set_write_disables(const struct intel_renderbuffer *irb,
return disables;
}
-static unsigned
-irb_logical_mt_layer(struct intel_renderbuffer *irb)
-{
- return physical_to_logical_layer(irb->mt, irb->mt_layer);
-}
-
static bool
do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
struct gl_renderbuffer *rb, unsigned buf,
@@ -799,6 +782,8 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
!brw_is_color_fast_clear_compatible(brw, irb->mt,
&ctx->Color.ClearColor))
can_fast_clear = false;
+ const unsigned layer = intel_miptree_physical_to_logical_layer(
+ irb->mt, irb->mt_layer);
const bool is_lossless_compressed = intel_miptree_is_lossless_compressed(
brw, irb->mt);
@@ -865,7 +850,7 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
blorp_batch_init(&brw->blorp, &batch, brw);
blorp_fast_clear(&batch, &surf,
(enum isl_format)brw->render_target_format[format],
- level, irb_logical_mt_layer(irb), num_layers,
+ level, layer, num_layers,
x0, y0, x1, y1);
blorp_batch_finish(&batch);
@@ -888,7 +873,7 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
blorp_clear(&batch, &surf,
(enum isl_format)brw->render_target_format[format],
ISL_SWIZZLE_IDENTITY,
- level, irb_logical_mt_layer(irb), num_layers,
+ level, layer, num_layers,
x0, y0, x1, y1,
clear_color, color_write_disable);
blorp_batch_finish(&batch);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 09204ec..69f7c5d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -776,6 +776,20 @@ intel_depth_format_for_depthstencil_format(mesa_format
format);
mesa_format
intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
+static inline unsigned
+intel_miptree_physical_to_logical_layer(const struct intel_mipmap_tree *mt,
+ unsigned physical_layer)
+{
+ if (mt->num_samples > 1 &&
+ (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
+ mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS)) {
+ assert(physical_layer % mt->num_samples == 0);
+ return physical_layer / mt->num_samples;
+ } else {
+ return physical_layer;
+ }
+}
+
/** \brief Assert that the level and layer are valid for the miptree. */
static inline void
intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
--
2.5.5
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
