Hi Altug and Jacob,
Yes, the most recent Visual Studio we are actively supporting is 2015. We
will support 2017 with an upcoming release but as you note Jacob, Boost and
other dependencies are still catching up themselves.
Jacob, Boost 1.64 is not officially supported but great to hear it is
work
Hello Daniel,
No, the storage is non-volatile. The script only needs to be run when
updating the FPGA.
Regards,
Derek
On Thu, Jul 6, 2017 at 9:40 PM, Cho, Daniel J (332C) via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hello –
>
>
>
> In order to load a custom FPGA, you run the python scr
Hello all,
The release candidate of UHD version 3.9.7 has been tagged and is available
for testing. This is an update to the Long Term Support series and is
planned to be released next Monday, the 17th.
The tag for this release candidate:
https://github.com/EttusResearch/uhd/releases/tag/003_009_
Hello Brais,
The gain values for USRPs are indexed from 0 dB gain being minimum gain up
to the device's maximum. Usually this means that 0 dB of gain is actually a
large amount of attenuation or loss through the RX chain. The same is true
for TX. It doesn't surprise me that you are seeing those va
Hello Brandon,
How did you install UHD and GNU Radio? When you say that the USRP is not
receiving the waveform, do you see just noise or does the application not
even start? What file was missing, there should definitely not be anything
missing from those versions.
I recommend ensuring that uhd_u
Hi Bradon,
The TwinRX should show up as a TwinRX in the RX slot and an unknown
daughterboard in the TX slot. This is a cosmetic issue which we're aware of.
It is possible that you have a revision B TwinRX which has a newer ID than
is supported by your version of UHD. Can you please post the full
Hello all,
The 3.9.7 release of UHD has been posted. This is an update to the Long
Term Support series. There was one commit between the release candidate and
the final release. This added some safety checks to the
uhd_images_downloader script when using custom destination directories.
The tag fo
Hello Altug,
The CIC can be programed to decimate by a range of integer amounts. If the
ratio is 20 (50 MHz sampling rate, 2.5 MHz output rate) then both half
bands will be used (divide by 2*2) and the CIC will decimate by 5. Odd CIC
rates have poor filter roll off compared to even rates.
Derek
Hello all,
The release candidate of UHD version 3.10.2.0 has been tagged and is
available for testing. There have been no API breaking changes necessary
since the last release but a small ABI change means we are incrementing the
ABI number. Updated FPGA and firmware images have been uploaded.
The
Hello,
To get time and frequency alignment on a pair of E31xs you can supply the
1PPS to both units. The example programs do not all support setting the
time source.
http://files.ettus.com/manual/page_usrp_e3x0.html#e3x0_hw_sync
Here is an example which supports setting the time source, you can m
Hi Jong,
Marcus Leech and Marco have both offered good advice on testing the
frequency stability of the B210 against outside references. Have you tried
either?
Marcus Muller also asked for additional information about your test setup.
Regards,
Derek
On Wed, Jul 26, 2017 at 2:04 AM, john liu via
Hello Altug,
If you tune using the tune request with a DSP policy of MANUAL and DSP
frequency of 0.0 then yes, that channel's CORDIC will not alter the samples.
A policy of NONE will leave the DSP in the last configured state, so it is
better to be explicit.
Regards,
Derek
On Wed, Jul 26, 2017
Hello,
Unfortunately the phase offset between channels on separate E31xs is not
repeatable between tunes or runs. In order to use multiple E31xs for
beamforming or other applications needing known phase offsets it is
necessary to supply an external reference signal and use that to measure
the offs
Hello Christian,
Your configuration of the LO sharing is all reasonable. You are not using
timed commands so you will not get repeatable phase offsets between the
channels due to the DDC's CORDIC and the RX frontend's IF downconverter not
being synchronously reset. The call to set_rx_freq for each
Hello Anuja,
That zip contains the USB driver for the B210, it is the same as the B200.
If you encounter an error message then unplug and replug the B210. This is
a non-fatal error that is seen occasionally with different Windows versions.
Regards,
Derek
On Mon, Jul 31, 2017 at 11:54 AM, Anuja K
Hello Nauman,
I assume that you are using the X310 rather than the E310.
It is not possible by default to use PCIe for configuration and control and
then to use the SFP+ connections with Aurora for the sample streaming. The
hardware could technically support such a configuration, but it would
req
Hello all,
The 3.10.2.0 release of UHD has been posted. This is an update to the main
series of releases. There were four commit between the release candidate
and the final release. All were documentation updates except for an
improvement to the query_gpsdo_sensors utility.
The tag for this relea
Hello Mark,
rx_samples_to_file will only receive a single channel. It is a minimal
example.
Try:
rx_multi_samples --channels 0,1
This will receive two channels, a pair of UBXs only has one RX channel per
daughterboard so UHD can infer the sub device specification. The default
sample rate is 100
Hello Adhitha,
If you are connecting only one USRP at a time directly to the computer and
see one work and one not then my first guess would be that the IP address
has changed on the second one. Try running uhd_find_devices, this will work
if the IP address is different but still on the same subne
Hi Mark,
Unfortunately you're up against the limits of the included examples. There
are no UHD only examples which store multiple channels of samples to a
file. The rx_multi_samples shows the steps involved in setting up the
channels, but doesn't implement the functionality shown in
rx_samples_to_
Hi Adhitha,
I'm glad that's worked for you.
Best regards,
Derek
On Tue, Aug 1, 2017 at 4:19 PM, Adhitha Dias
wrote:
> Hi Derek,
>
> I tried with the large netmask. Now it's working. Thank you so much for
> the help. Really appreciate it!
>
> I am using UHD version 3.10.1.0 in Ubuntu 16.04.2 OS
Hi Dave,
You're exactly right, there is a decimation operation between the raw ADC
IQ samples and the samples which can be streamed *continuously* across a 1
Gigabit link.
It is very similar to the X310 where the frontend passes the full rate
samples to a DDC chain.
https://github.com/EttusResearc
Hello Daniel,
There is no check in your code to confirm that the time is correctly set.
The 1PPS signal should be a square wave rather than a sine wave. It is a
logic signal rather than an RF one and the sync port is designed to handle
it.
http://files.ettus.com/manual/page_usrp_e3x0.html#e3x0_hw_
Hi Mark,
I've added back on the list, it's useful to keep everyone in sync with
progress.
The WX FFT only takes one input but the QT Frequency Sync has a
configurable number of inputs. In general the QT GUIs are being promoted
over WX.
Regards,
Derek
On Tue, Aug 1, 2017 at 7:40 PM, Mark Koenig
Hi Konstantin,
Mike's solution is one of the common answers. Mounting a network share or
remote file system are nice to streamline the process. Our application note
on developing with the E310 has an example of using sshfs to mount a
directory from a host computer onto the E310.
https://kb.ettus.c
Hi,
Sorry, I spoke poorly there. set_time_unknown_pps will fail if it does not
see a 1PPS edge within a 1+epsilon second window. However, because you were
using a sine wave the exact time that the "edge" of the pulse could vary.
When distributing a time reference a fast rising edge is key to getti
Hello Snehasish,
The UHD examples contain all the code to receive a stream of samples at
that rate. What have you tried? We may be able to help better if you
explain what is not working. 50 MS/s is not too high of a load so most
recent computers should have no problem receiving that much data over
Hello Konstantin,
The download definitely works on Windows, Mac, and Linux so there must be
some issue with your VM that is causing the issue. That is probably beyond
what we can help with.
On Windows you can use 7zip to extract the xz archive and win32diskimager
for writing the filesystem image
Hi Konstantin,
We have no way of knowing what device the SD Card will enumerate as. There
are many guides online for using utilities like fdisk and dmesg to find the
name of the device.
Using Windows or Linux you will need to remove the micro SD card and use a
USB to micro SD card adapter to moun
Hello Jorge,
The Octoclock is sold in two versions, one with an internal GPSDO and one
that requires an external source.
The X310 and X300 both do not support daisy chaining. There are a few
issues with it, one of the key ones being propagation delay. If the 1PPS
signal was passed from one unit t
Hello,
Yes, a micro SD card adapter is needed. I'm going to add to our
documentation to highlight that point. There is no way to overwrite the
entire SD remotely. This is true for nearly every embedded system.
We do not have any recommended micro SD card adapter. There are many from
good brands s
Hello Jon,
As you have found in the documentation and see in the output of
uhd_usrp_probe, the XCVR2450 is not supported on the X3x0 family. We are
sorry this is true, but we do not have any current timeline for adding this
support nor do we have any advice right now to give for what changes would
Hi Janos,
The problem is that the single rx_streamer is trying to time align the
samples from the four USRPs, but the onboard clocks are not aligned so it
is not finding samples from the same moment. Are you sharing 10 MHz and
1PPS references to all the USRPs? If so you will need to set the clock
If you do not need any time synchronization then you can use four separate
rx_streamers.
The time source (and clock source) will default to internal. Do you have
MIMO cables between the N210s? Given that you have four that won't save you
from having to have a separate external 10 MHz and PPS to sy
Hello Daniele,
If you run uhd_usrp_probe you will see a list of the supported frontends.
The example is for the TVRX2 daughterboard which you are probably not
using. The most common subdev specifications for a single X310 are "A:0
B:0" (First channel of each daughtercard) and "A:0 A:1 B:0 B:1" (E
Hello Dave,
This commit added the EEPROM IDs for the updated UBX version.
https://github.com/EttusResearch/uhd/commit/f5a082fd3841571d2a53a9e677b5dfe6d653bd94
It was added August 22nd and 3.9.5 has it. I believe there have been a few
improvement changes since then which are on the 3.9 branch, but
Hello Snehasish,
Here is the performance data for the UBX daughtercard and X3x0. The
sensitivity changes with frequency and gain.
http://files.ettus.com/performance_data/ubx/UBX-without-UHD-corrections.pdf
Regards,
Derek
On Wed, Aug 16, 2017 at 8:14 AM, Snehasish Kar via USRP-users <
usrp-users@
Try 200MS/s. The FPGA can only decimate integer amounts from the ADC rate,
which is 200MS/s.
On Tue, Aug 22, 2017 at 5:15 PM, Snehasish Kar via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hello
> I am trying to receive gsm 1800 band using NI USRP 2954R, but when I am
> trying to set the sam
Hello Koyel,
This is a fundamental problem that increasing sample rate takes more
processing power to handle but provides more bandwidth of spectrum. How
wide is the signal you need to process? The general recommendation is that
you sample at 1.25 times your bandwidth. This provides 20% more spect
Hello,
Can you please paste a copy of the full output, including the command, for
uhd_usrp_probe? That will include a lot of information which we can use to
offer advice.
Thanks,
Derek
On Wed, Aug 30, 2017 at 11:21 AM, L TP via USRP-users <
usrp-users@lists.ettus.com> wrote:
>
> Hi List,
> I'm
Hello Ali,
You have not set a gain value in your command. You can check the GRC
example to find the default gain or try values until you see a strong
signal.
Regards,
Derek
On Sat, Sep 9, 2017 at 9:59 AM, Ali The GREAT! via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Dear all,
>
> I insta
Hello Joshua,
The default FPGA image now has two DDCs which each have two DSP chains. The
message you link to is from 2014 and we've substantially updated the
contents of the FPGA since then. Currently the TwinRX is the primary
daughtercard making use of these additional DDC chains as the others a
That assertion is protecting a register in the Radio Block on the FPGA. You
could try modifying that area of the logic which is counting the outputted
samples as they are packetized. I do not believe that other areas of the
code would be impacted (other than that assertion in the host code of
cours
Hi Jason,
Adding FIFOs adds buffering which helps with any transient changes in
throughput, such as over the 10 GigE connection. It gives the flow control
more room to work with before an overflow occurs (on receive). On the
transmit side the DMA FIFO usually fills that role.
On Fri, Sep 29, 2017
Hello Brais,
The HDL design does have a top block and is composed of usefully divided
sub blocks. It is not however designed using the graphical Vivado workflow,
but a source based one. Here is the top block:
https://github.com/EttusResearch/fpga/blob/maint/usrp3/top/e300/e310.v
Your application
Hello Mark,
It has been some time since I have looked at the probe routine in the 3.8
version of UHD, but it sounds like the discovery packets are having routing
problems. Do you have an N210, N200, or USRP2 anywhere on the network?
We can probably give some assistance to discovering the root cau
Hello,
The requested sizes do change a little during the initialization. Also the
settings are not persistent across reboots of your host computer so need to
be re-appled each time you restart or changes made to other configuration
files to make them persistent.
Can you confirm which sizes you ar
Hi Mark,
I'm glad to hear you were able to update to 3.9. Retuning the UBX takes
approximately 500 usec. This varies based on how far the internal VCO needs
to tune and if there is a band crossing.
A dwell time of 5 seconds (5,000 msec) should be four orders of magnitude
more than is needed to ge
Hello Kevin,
No, the N200 and B200 do not change the electrical transport modes based on
the frequency or bandwidth requested by the application, there is no need.
The 12 and 14 digital bits are available at all frequencies. The actual
effective number of bits out to the host depends on the ADC pe
Hi Kevin,
It is 12 bits each for I and Q, a total of 24 bits per complex sample pair.
It is usual for SDRs to list the resolution of the ADC which is then dual
channel for the I and Q.
https://www.ettus.com/content/files/b200-b210_spec_sheet.pdf
Regards,
Derek
On Fri, Oct 13, 2017 at 12:29 PM, K
Hi Janos,
What daughtercards are you using? Can you include the console output of
your program when it runs? It looks like you have useful log messages.
Thanks,
Derek
On Tue, Oct 17, 2017 at 11:32 AM, Janos Buttgereit via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hello everybody,
>
> I
Hello Brais,
Sorry for the long delay. Yes, the B210 has a Spartan 6 which is not
supported by Vivado so the design uses ISE. This, and the smaller size of
the B210's FPGA, is why RFNoC support has not been added to it. All third
generation USRPs support RFNoC and so will all planned future USRPs.
Hi Luca,
Any external 10 MHz and 1PPS source will work. The 1PPS is basically a DC
signal so it is best to have a buffer amplifier to split it, but if just
going to two USRPs you may be able to get away with using the RF power
divider as well.
The required signal levels are posted in the user man
Hi Jason,
The command message handling in the USRP source in GNU Radio is a bit
interesting. The command may contain many pairs of key->value, most of
which end up in a call to their own handler. There is a debug message
printed for each of these handlers if you have GNU Radio debug messages
enabl
Hi Wahhab,
It sounds like you are expecting a configuration which is not possible.
With an ADC sampling rate of 2 MS/s complex your application will receive
valid information about 2 MHz of bandwidth. Setting the analog bandwidth to
2 MHz or 56 MHz will not change this. In order to receive inform
The error checking of the parameter range will happen inside of UHD rather
than in the GNU Radio wrapper. The existing check is only for the type of
the parameter, in the gain case a numerical value is supplied so it passes
the check.
The first command will result in a tune to 2.4 GHz.
The second
Hello Dragoslav,
What you are seeing is expected and correct. With the multi_usrp interface
the set_tx_freq function does a series of actions for you.
1) Calculate a target RF frequency, taking into account any LO offset
requested
2) Call a function to set the RF frequency to this target and then
Hello Wahhab Albazrqaoe,
It is certainly possible to configure each USRP to be tuned to a different
frequency and to be synchronized closely in time. A 1 Gigabit Ethernet
connection can carry approximately 25 MS/s of 16 bit samples and 50 MS/s of
8 bit samples. We do not support sending 4 bit samp
Hello Wahhab,
I do not know about using the MIMO cable between a USRP2 and a N2x0, the
USRP2 became end of life before I started at Ettus. I think it would work,
but cannot test it myself. Others at Ettus may know the answer.
You will need at least two 1 Gigabit connections to your host computer.
Hello Ivan,
The rule of thumb is that the digital filters are flat over 80% of the
passband. A good start would be to exclude the first and last 10% of each
FFT and reduce your frequency step size to 80% of the sample rate. This
will flatten your spectrum considerably.
USRPs have a calibration ro
I've added back on the mailing list, just include usrp-users@lists.ettus.com
as a to: address. If you use reply-all in the future it will keep the list
up to date.
The "n" value needs to be adjusted now that the step size is 20% smaller.
On Thu, Nov 16, 2017 at 9:34 AM, Ivan Zahartchuk
wrote:
>
Hi Chad,
To add to what Neel said, no matter the FPGA image or Ethernet type a USRP
cannot be accessed from two computers at the same time. The device is
claimed as the first action when a connection is made to it by a program.
Regards,
Derek
On Fri, Nov 17, 2017 at 1:08 AM, Neel Pandeya via USR
Hello Chad,
You'll need a program which can receive from both channels at once. The
claiming means that two processes cannot access the same USRP at the same
time. The rx_multi_samples shows receiving two sample streams on the same
frequency and the same rate. You'll likely need to write your own
Hello Fabrizio,
Have you tried running the benchmark_rate example included with UHD? That
can test if there is any issue sending data at that rate to the USRP.
uhd_siggen is also a good test as it uses GNU Radio so can check that the
rate continues to work from within GNU Radio.
If both of those
Hello Ale,
That left shift is intentional behavior. Here is the comment on that line
of code.
https://github.com/EttusResearch/uhd/blob/maint/host/include/uhd/utils/soft_register.hpp#L100
When you say you "tried to run query_gpsdo_sensors, that one was not
finalized" do you mean that it was not c
Hi Ale,
I've added back on the list. It's usually best to keep the list included so
you can get faster responses from a larger group of experienced people.
That example isn't installed into the default PATH like the core UHD
programs are. The binary can be found at (by default on Ubuntu)
/usr/loc
Hello Anon,
I can confirm that your issue is due to software and not a hardware issue.
The fix is released on the maint branch and will be out on the master
branch very shortly.
https://github.com/EttusResearch/uhd/commit/f76762c6e9cd7d7e308c589d57cb89
1eda45a4e8
Can you please apply the one char
Hello Andy,
The LO source is for an external or internal RF source and is fed directly
to the mixers. You are looking for the set_clock_source call which will
allow you to set the USRP to use an external 10 MHz reference.
Regards,
Derek
On Thu, Jan 25, 2018 at 7:53 PM, Andrew Thommesen via USRP-
Hi Tarik,
Your steps are based on the misunderstanding of how the image loading
occurs in each of these scenarios.
When using PCIe the FPGA will always be reloaded from the host computer.
Every program you run using the PCIe link needs the
"fpga=/path/to/image.lvbitx" string added to the device a
Hi Tarik,
The USRP source in GNU Radio has a spot for specifying device arguments.
The osmocom_fft application has a "--args" option the same as the UHD
utilities. There is not currently the ability to specify a custom default
FPGA image but it is a feature we agree would be useful.
Regards,
Dere
Hi Tarik,
I'm glad you got that working. Yes, modifying UHD is certainly a way that
you can specify a custom file. I didn't mention it because the device
arguments method works in nearly all software. For instance, the path to
the bitstream can certainly be supplied as a parameter in GNU Radio
Com
Hello Jonathan,
The gain setting in the USRPs are indexed from minimum gain. On most this
means a gain of 0 is actually an attenuation of the signal. The N210's gain
range is based on what amplifiers and attenuators are on the daughterboard
that is installed. The ranges aren't calibrated to be ali
Hello Mark,
Yes, people have used external Thunderbolt to 10 GigE SFP+ adapters
successfully in the past.
https://www.youtube.com/watch?v=w9wlKYDEOUU
I do not have up to date information about the level of performance to be
expected in such a setup however. In the video Balint is streaming at 100
Hello Fabian,
The set_rx_bandwidth() function does not work with the TwinRX. If the value
returned by get_rx_bandwidth is changing then that is a bug which I will
look into. It is used for the B2xx and E3xx series, as well as the brand
new N310, which have RFICs with programmable bandpass filters.
Hello Akshatha,
What ethernet connection are you using between the USRP and the host
computer? The IP address of the USRP will depend on which SFP+ port and
what FPGA image you are using.
http://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_setup_network
Regards,
Derek
On Thu, Feb 15, 2018 at
Hi Dan,
The E310/E312 has the switchable set of receive and transmit filters which
the B2xx does not. This will impact the noise figure due to the additional
losses of the switches and filters. As with most receivers an external LNA
and filter matched to a frequency of interest will reduce the tot
Hello,
The tuning time is approximately 5 ms, which is why the example uses that
number. The example should work the same on either Windows or Linux. What
version of UHD are you using on Windows which does not include it?
Are you seeing any streaming errors on Windows?
Regards,
Derek
On Mon, Fe
Hello,
Please can you keep your emails in a single thread so it is easier to read.
The goal with the frequency hopping example is to instantly jump between
frequencies. Normally those 3-5 ms of tuning would be dead time, no
meaningful signal could be received. By using the RF synthesizers of both
I'm not sure how you are responding, but it is still not threading
correctly. Thanks for trying though.
I would not expect the C API to make a performance difference like that
since it is only a wrapper. Are you still using timed commands? If not then
the additional overhead of sending commands fr
Hello Joe,
The source code for both the driver and FPGA HDL are hosted on GitHub. Here
are links to them:
https://github.com/EttusResearch/uhd
https://github.com/EttusResearch/fpga
The manual has a short section about sample rate options:
http://files.ettus.com/manual/page_general.html#general_sa
Hello Andy,
You can use the standard UHD streamer functions to do a burst reception in
GNU Radio with the number of samples set to 1024.
Regards,
Derek
On Thu, Mar 1, 2018 at 8:54 AM, Andrew Thommesen via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi,
>
>
> Is it possible to use gnuradio
Hello Professor Mercado,
In addition to Neel's link for the Octoclock, here is one for the B210.
http://files.ettus.com/manual/page_usrp_b200.html
Also an application note about getting started with the C++ UHD API to
USRPs.
https://kb.ettus.com/Getting_Started_with_UHD_and_C%2B%2B
Regards,
Dere
Hello,
You are receiving the maximum possible sample rate. The TwinRX is able to
provide two channels of data compared to the usual 1 per daughterboard
because it uses the 200 MS/s ADC to do real mode sampling on the two
channels. The FPGA then does a conversion to 100 MS/s Complex samples for
eac
Hello,
Setting the LO source does not tune the synthesizers so the actual command
duration should be very short. How are you measuring the durations?
I looked at why the twinrx_freq_hopping demo is not built by default on
Windows and it is because of an optional feature which requires a library
w
Hello Kushagra,
I can't. I've never looked into the details of digital video signals and so
I would be starting where you are. As I said, I would start by trying to
run the existing code and getting it working. From there you can research
online for information about the video signals inside your
Hello Zhongyuan Zhao,
Doing FPGA development on the X310 almost never requires interacting with
the ZPU. The ZPU is used with the UHD driver to provide underlying system
support. The recommended way to add DSP operations to the FPGA is to
construct or modify RFNoC blocks.
I'd recommend reading the
Hello Andrew,
Are you starting the streaming with timed commands?
Regards,
Derek
On Mar 8, 2018 7:32 PM, "Andrew Thommesen via USRP-users" <
usrp-users@lists.ettus.com> wrote:
Hi all,
I have an x310 with a twinRx and would like to process coherent,
time aligned data within the FPGA. However,
The stream command object has a field for a time spec of when to start
streaming and a boolean flag for whether to make use of that time spec.
http://files.ettus.com/manual/structuhd_1_1stream__cmd__t.html
Here we can see it used in an rx example.
https://github.com/EttusResearch/uhd/blob/maint/ho
, Nebraska 68588-0115
>
>
> On Thu, Mar 8, 2018 at 3:27 PM, Derek Kozel via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> The stream command object has a field for a time spec of when to start
>> streaming and a boolean flag for whether to make use of that ti
gt;>>
>>> Thanks
>>>
>>> Zhongyuan Zhao
>>>
>>> PhD Candidate,
>>> Department of Computer Science & Engineering,
>>> University of Nebraska-Lincoln
>>> Office Hour: WF 9:30-10:00am, Avery Hall 12,
>>> Suite 117, S
Hello,
Yes, the same use of timed commands applies for the transmit side tuning.
Just use set_tx_freq instead of set_rx_freq. The timed command
functionality applies to many features on the X310 such as setting the
gain, selecting antennas, and other commands.
Regards,
Derek
On Thu, Mar 15, 2018
Hello Jose,
The B210's two channels use a common local oscillator so cannot tune to two
separate analog frequencies.
http://files.ettus.com/manual/page_usrp_b200.html#b200_fe
However if your two center frequencies are relatively close together, such
that the minimum and maximum frequencies of you
Hello Lucas,
I'll address your last question. The limitation is a hardware one as the
FPGA is connected to the AD9361 using the CMOS interface and the bandwidth
is split between the channels. This cannot be changed on the B210.
Regards,
Derek
On Thu, Mar 15, 2018 at 11:57 AM, Lucas Val Terrón vi
Hello Adams,
Yes, the TwinRX Rev A and B work with RFNoC, but the rfnoc-devel branch may
currently have some regressions. We are in the process of updating the
rfnoc-devel branch with many changes from the master branch including
support for the TwinRX Rev C. We will be doing regression testing of
Yes, the data is timestamped. By default it will be times relative to when
the USRP was first turned on, but the set_time_next_pps function can be
used to align the internal time with an external or GPSDO based reference.
http://files.ettus.com/manual/page_sync.html#sync_time
There are examples f
Hello Matis,
UHD uses RFNoC internally at all times since the 3.10.0.0 release. The XML
files are needed for standard operation. It does not expose the full API or
set of features unless the rfnoc-devel branch is used.
Regards,
Derek
On Fri, Mar 23, 2018 at 6:05 PM, Matis Alun via USRP-users <
u
at 6:23 PM, Rob Kossler wrote:
> This necessity for setting UHD_RFNOC_DIR should probably be added to the
> UHD manual.
>
> On Fri, Mar 23, 2018 at 2:15 PM, Derek Kozel via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hello Matis,
>>
>> UHD us
f one was installed using apt or your
>> package manager then it should be removed the same way.
>>
>> Regards,
>> Derek
>>
>>
>> On Fri, Mar 23, 2018 at 6:23 PM, Rob Kossler wrote:
>>
>>> This necessity for setting UHD_RFNOC_DIR should probab
Hello Louis,
Yes, the schematics are being prepared for posting. I don't know
specifically when that will be completed. Unlike the X310 the GPSDO is
always installed with the N310.
The GPSDO is a Jackson Labs LTE Lite.
http://jackson-labs.com/index.php/products/lte_lite
The 25 MHz TCXO is a Crys
Hello Juan,
Right now RFNoC development requires Vivado 2015.4 and the rfnoc-devel
branch. We are in the process of updating the rfnoc-devel branch to include
the changes from the master branch, including Vivado 2017.4 support.
Regards,
Derek
On Tue, Mar 27, 2018 at 4:33 AM, Juan Francisco via U
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