Hello Zhongyuan Zhao, Doing FPGA development on the X310 almost never requires interacting with the ZPU. The ZPU is used with the UHD driver to provide underlying system support. The recommended way to add DSP operations to the FPGA is to construct or modify RFNoC blocks. I'd recommend reading the application note on RFNoC development and/or watching this video which covers much the same content.
https://kb.ettus.com/Getting_Started_with_RFNoC_Development https://www.youtube.com/watch?v=j-EfyPVpaJ8 In short, development requires a license to Vivado 2017.4 and the X310s have JTAG and Chipscope capability exposed to Vivado via the frontpanel USB socket. We'd be happy to answer any questions you have about RFNoC development. Regards, Derek On Thu, Mar 8, 2018 at 5:50 PM, Zhongyuan Zhao via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > > I wanna customize the USRP FPGA code on X310/N310. I found out that FPGA > code is structured as a softcore ZPU controlling peripherals. > > The FPGA code can be developed on ISE and Vivado, and the firmware of ZPU > can be compiled via ZPUGCC. But this seems to be insufficient for > development, especially debugging. > > What is the recommeded workflow/tools to debug the FPGA and firmware code? > Is there any JTAG/emulator/simulator for ZPU so that we can step into the > code, and examine the registers? > > Does ZPU provide features similar to RS232 offered by many embedded system > to print out check points in the program? > > Thanks! > > Zhongyuan Zhao > > PhD Candidate, > Department of Computer Science & Engineering, > University of Nebraska-Lincoln > Office Hour: WF 9:30-10:00am, Avery Hall 12, > Suite 117, Schorr Center, > Lincoln, Nebraska 68588-0115 > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >
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