Hello Joe, The source code for both the driver and FPGA HDL are hosted on GitHub. Here are links to them: https://github.com/EttusResearch/uhd https://github.com/EttusResearch/fpga
The manual has a short section about sample rate options: http://files.ettus.com/manual/page_general.html#general_sampleratenotes The B200mini's decimation is provided by its DDC. The host controls are in this file: https://github.com/EttusResearch/uhd/blob/7ac01c7f979aab8fac5e62f596ff0af52cedec40/host/lib/usrp/cores/rx_dsp_core_3000.cpp You are probably most interested in this function: https://github.com/EttusResearch/uhd/blob/7ac01c7f979aab8fac5e62f596ff0af52cedec40/host/lib/usrp/cores/rx_dsp_core_3000.cpp#L148 On the FPGA side https://github.com/EttusResearch/fpga/blob/maint/usrp3/lib/dsp/ddc_chain.v Did you have specific questions? Regards, Derek On Mon, Feb 26, 2018 at 5:07 PM, Stern, Joseph via USRP-users < usrp-users@lists.ettus.com> wrote: > Dear USRP users: > > > > We have been trying to understand the low-level details of the USRP > architecture (namely, for the B200mini); there seems very little explicit > insight provided on the Ettus web site into how decimation is performed in > the FPGA (and commanded from the driver side). I also cannot locate the > open-source and freely available FPGA code. Could someone assist me in > gaining this insight? > > > > Thank you very much! > > > > Joe Stern > This message and any enclosures are intended only for the addressee. > Please > notify the sender by email if you are not the intended recipient. If you > are > not the intended recipient, you may not use, copy, disclose, or distribute > this > message or its contents or enclosures to any other person and any such > actions > may be unlawful. Ball reserves the right to monitor and review all > messages > and enclosures sent to or from this email address. > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >
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