Hi Dave, You're exactly right, there is a decimation operation between the raw ADC IQ samples and the samples which can be streamed *continuously* across a 1 Gigabit link. It is very similar to the X310 where the frontend passes the full rate samples to a DDC chain. https://github.com/EttusResearch/fpga/blob/maint/ usrp2/sdr_lib/ddc_chain.v#L119
I believe, but am unable to check at the moment, that the full 100 MS/s can be received in bursts, the limit of each burst being the accumulated buffers in the FPGA combined with the ethernet link. There are other operations performed on the IQ samples in the frontend, you can see them in this HDL file. Some of the compensations can be set to not influence the samples, but others could not be disabled without rebuilding the FPGA image. https://github.com/EttusResearch/fpga/blob/maint/usrp2/sdr_lib/rx_frontend.v Usually that is not desirable though as these corrections generally improve the spectrum. Regards, Derek On Tue, Aug 1, 2017 at 3:18 PM, Dave NotTelling via USRP-users < usrp-users@lists.ettus.com> wrote: > What happens to samples between the ADC and receiving them from UHD? > Also, is there any way to get the raw IQ off of the ADC itself? I feel > like there isn't only because the ADC (to the best of my knowledge) runs at > 100 MSPS which is too high a rate to send over the 1 Gb/s link. > > Thanks! > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >
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