Hi Tarik, Your steps are based on the misunderstanding of how the image loading occurs in each of these scenarios.
When using PCIe the FPGA will always be reloaded from the host computer. Every program you run using the PCIe link needs the "fpga=/path/to/image.lvbitx" string added to the device arguments. The image loading is very fast compared to other methods. For example: uhd_usrp_probe --args="fpga=/path/to/image.lvbitx" When using JTAG an image is loaded into RAM on the FPGA. This will be overwritten if PCIe is used and forgotten (the RAM will clear) when the device is turned off. This is useful for rapid testing when using Ethernet connections since JTAG is faster than writing to flash, and for recovering when an image with an error has been written to the flash. When using the uhd_image_loader the image is written to flash and will be used the next time the device is turned off and on again. This is useful for loading a persistent image when using the Ethernet interfaces. PCIe will still load and use an image from the host every time. Can you please try the uhd_usrp_probe with the device arguments specifying the FPGA image to use? As for 2x10 GigE vs PCIe, No, they do not have the same throughput. The PCIe is equivalent to 1x 10 GigE. In order to get the full bandwidth of the X3x0, which is 2x 200 MS/s on receive, you would need to use both 10 GigE connections. https://kb.ettus.com/X300/X310#Choosing_a_Host_Interface Regards, Derek On Tue, Jan 30, 2018 at 10:01 AM, Tarik Kazaz via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello Martin, > > I hope I am replying now correctly (I am using reply all to you and > mailing list). > I am still not able to flash RFNoC bit stream on FPGA. Here is what I am > doing: > > 1. First step - Check status of device > > Call: uhd_usrp_probe > Output: [INFO] [X300] Using LVBITX bitfile > /home/cas-sdr/rfnoc/share/uhd/images/usrp_x310_fpga_XG.lvbitx... > ... > | | | RFNoC blocks on this > device: > | | | > | | | * DmaFIFO_0 > | | | * Radio_0 > | | | * Radio_1 > | | | * DDC_0 > | | | * DDC_1 > | | | * DUC_0 > | | | * DUC_1 > > 2. Second step: Load new FPGA image - usrp_x310_fpga_RFNOC_XG.lvbitx: > > Call: uhd_image_loader > --args="type=x300,RESOURCES=RIO0" --fpga-path="/xyz/xyz/rfnoc/sh > are/uhd/images > > /usrp_x310_fpga_RFNOC_XG.lvbitx" > > Output: > [INFO] [UHDlinux; GNU C++ version 4.8.4; > Boost_105400; UHD_4.0.0.rfnoc-devel-409-gec9138eb] > [INFO] [NIRIO] rpc_client stopping... > [INFO] [NIRIO] rpc_client stopped. > [INFO] [NIRIO] rpc_client stopping... > [INFO] [NIRIO] rpc_client stopped. > [INFO] [NIRIO] rpc_client stopping... > [INFO] [NIRIO] rpc_client stopped. > [INFO] [NIRIO] rpc_client stopping... > [INFO] [NIRIO] rpc_client stopped. > Unit: USRP X310 (3114FC4, RIO0) > FPGA Image: > /xyz/xyz/rfnoc/share/uhd/images/usrp_x310_fpga_RFNOC_XG.lvbitx > -- Loading XG FPGA image (this will take > 5-10 minutes)...[INFO] [NIRIO] rpc_client stopping... > [INFO] [NIRIO] rpc_client stopped. > > ....After few minutes I get: > successful. > Power-cycle the USRP X310 to use the new > image. > [INFO] [NIRIO] rpc_client stopping... > [INFO] [NIRIO] rpc_client stopped. > > 3. Third step: power cycle USRP and PC > > Call: sudo /usr/local/bin/niusrprio_pcie stop > Power cycle USRP > Power cycle PC > > > 4. Forth step: power up USRP and PC, check status of USRP > > Call: Power UP USRP > Power UP PC > uhd_usrp_probe > Output: [INFO] [X300] Using LVBITX bitfile > /home/cas-sdr/rfnoc/share/uhd/images/usrp_x310_fpga_XG.lvbitx... > ... > | | | RFNoC blocks on this > device: > | | | > | | | * DmaFIFO_0 > | | | * Radio_0 > | | | * Radio_1 > | | | * DDC_0 > | | | * DDC_1 > | | | * DUC_0 > | | | * DUC_1 > > > So, what I am doing wrong? > > In general I would like to ask you do suggest usage of PCIe or 10GBe > interface with USRP X series? > > In terms of throughput between PC and USRP, PCIe and 2x 10GBe interface > should be same or I am wrong? > > I am asking this because I am working with UWB sampling and compressed > sampling (high throughput is important, especially for Rx side) > My configuration of USRP consists of 2 UBX cards together with X310. > > Maybe I can try to flash usrp_x310_fpga_RFNOC_XG.lvbitx over jtag with > Xilinx tools. However, I do not think .lvbitx is supported with xilinx > tools. > > Thanks once again, > Kind Regards, > Tarik > > > > > > > > > > ________________________________________ > From: Martin Braun [martin.br...@ettus.com] > Sent: Tuesday, January 30, 2018 5:23 AM > To: Tarik Kazaz; 'USRP-users@lists.ettus.com' > Subject: Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images > > Tarik, > > please remember to keep responses on the mailing list, lest they get lost. > > Yeah, just add fpga=/path/to/image.lvbitx to your device args. > > -- M > > On 01/29/2018 09:56 PM, Tarik Kazaz wrote: > > Hello Martin, > > > > Could you provide me more detailed instruction, how to disable PCIe to > reload image. > > > > I think instead of .bit, I should flash it with .lvbit if I want to use > USRP > > over PCIe with RFNoC? Or I am wrong. > > > > Kind Regards, > > > > Tarik > > > > -----Original Message----- > > From: USRP-users [mailto:usrp-users-boun...@lists.ettus.com] On Behalf > Of Martin Braun via USRP-users > > Sent: maandag 29 januari 2018 20:46 > > To: usrp-users@lists.ettus.com > > Subject: Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images > > > > On 01/29/2018 07:37 PM, Tarik Kazaz via USRP-users wrote: > >> Hello everyone, > >> > >> > >> > >> I am just starting to use RFNoC and I am a bit confused with hardware > >> compatibility for RFNoC development. > >> > >> In order to describe my setup I will list items below: > >> > >> > >> > >> 1. I have NI USRP RIO (equivalent of X310 with integrated GPS > >> module) > >> > >> 2. I am connecting it with PC over PCIe interface > >> > >> > >> > >> I tried to flash USRP with RFNoC *usrp_x310_fpga_RFNOC_XG.bit* image. > >> However, after I power cycle USRP > >> > >> and execute *uhd_usrp_probe* seems that fpga is again flashed with NI > >> USRP as it contains *only DDCs, DMA and Radio* > >> > >> *RFNoC blocks*. > >> > >> > >> > >> In general I am confused what is a right RFNoC image for setup > >> consisting of USRP connected with PC over PCIe interface. > >> > >> Should I *use XG RFNoC FPGA images*? Are RFNoC images compatible with > >> PCIe interface? > > > > Yeah, but PCIe does reload images on every run. If you specify > fpga=/path/to/rfnoc_image.bit, it'll pick that. > > > > > > -- M > > > > _______________________________________________ > > USRP-users mailing list > > USRP-users@lists.ettus.com > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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