I recorded a complex signal file, I did it with HackRFONE, For sending on
USRP I want to use the int16 option as input, My question is how can
convert a complex float 32 signal to complex int 16 for USRP?
what's the relation between complex float 32 and complex int 32 in USRP?
I know that in USRP
RFNOC block folder and I was faced with error
not found...
> makefile_srcs:
> "${fpga_lib_dir}/blocks/rfnoc_block_correlate/Makefile.srcs"
On Wed, Jun 22, 2022 at 12:53 PM sp h wrote:
> Finally, I mention that, I found there is a bug in UHD 4.1.0.5 or UHD
> 4.2.0.0 when
RFNOC block folder and I was faced with error
not found...
> makefile_srcs:
> "${fpga_lib_dir}/blocks/rfnoc_block_correlate/Makefile.srcs"
On Sun, Feb 13, 2022 at 10:39 AM sp h wrote:
> Finally, I edited the RFNOC image core when I used the default RFNOC
> image core x30
DAC to the TwinRx.
>
> Sent from my iPhone
>
> > On Jun 19, 2022, at 9:44 PM, sp h wrote:
> >
> >
> > I have a daughterboard TwinRX in RF B in x300. When I use UHD and set
> the stream channel to 1 .
> > as TwinRX daughterboard is the only receive
When I want to build UHD 4.2.0.0 I faced with below warning.
> IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a
> Design_Linking license.
Building FPGA process cannot go to compile other IP cores and stays in
ten_gig_eth_pcs_pma IP and repeats...
For UHD v4.1.0.5 I had no p
I examine all of the code again and again but my problem is not solved
yet...
any RFNOC developer can not guide me?
thanks in advance
On Tue, Jun 14, 2022 at 11:21 AM sp h wrote:
> When I added ce clock domain to gain block and synthesized it, in Gnuradio
> it generates
> I at
's usually
> worth spending some time building a good testbench to make sure everything
> works the way you expect before you rebuild the FPGA.
>
> Wade
>
>
> On Sun, Jun 12, 2022 at 2:40 AM sp h wrote:
>
>> Is it possible that synthesis and generating bitstream in RFNO
When I added ce clock domain to gain block and synthesized it, in Gnuradio
it generates
I attached my source code in below, can anyone guide me? I emphasize that
I read the RFNOC FFT and replay blocks and according to them, I added ce
clocks...
FFT and replay block work successfully but for t
Is it possible that synthesis and generating bitstream in RFNOC blocks make
faster??!!!
I developed a custom RFNOC block, (I used example gain for RFNOC block) but
when I want to synthesize Verilog code It takes long about 2 hours...
For building the RFNOC bitstream image I used the below command:
how to add the .xci source to the Makefiles so the
> vivado scripts (which are called when I do "rfnoc_image_builder")
> synthesize it.
>
> Kind Regards,
> Maria
>
>
> El dom., 5 jun. 2022 18:50, sp h escribió:
>
>> Hi, You should not expect that integrate or a
Hi, You should not expect that integrate or add Xilinx IP core directly to
RFNOC blocks, Even If you be a master in Verilog...
If you see the UHD source code you will realize that UHD is an RFNOC
framework for USRP ...
For working with the RFNOC UHD framework you should know more details:
1)Please
:46 PM sp h wrote:
> Yes, I read all UHD 4 Docs and GRCON videos but do these blocks in image
> builder really work? I think they are not stable and have a bug ...
> Does anyone work with them? ... So I manually change the USRP image core.
> But in GUI I had ambiguity... So I ask.
&
When I want to customize RFNOC blocks, like adding an FFT block in
Gnuradio generate OOO?
When I change the RFNOC image core in USRP from the below link, the FFT
block does not work in Gnuradio, For the Gain block same problem...
https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
when I used uhd_usrp_probe it returns the RFNOC block list and static
connections between them. my question is what's means numbers in them? can
anyone guide me? I know that #X should be the numeric id of the RFNOC
block... I think number two is the number port? wich port is input wich is
output?
videos: Exploring RFNoC 4 with the UHD Python API -
> https://youtu.be/fbcxm7f-Tj0
> <https://www.youtube.com/watch?v=fbcxm7f-Tj0&t=0s> RFNoC 3 workshop video
> - https://youtu.be/VbODcrmpLaU
> <https://www.youtube.com/watch?v=VbODcrmpLaU&t=0s>
>
> Hope this helps,
when I examine RFNOC block that is in the below path, I am faced with a
wire ce_clk and ce_rst, but in rfnoc-example there is not a ce_clk.
uhd-4.1.0.5/fpga/usrp3/lib/rfnoc/blocks
Can anyone guide me ce clocks? why instead using rfnoc_chdr clk,
original blocks uses ce clock?
When I want to build the rfnoc-example that is in the UHD-4.1.05 folder I
am faced with the ce_clock error...
In this example, there is an Incompatibility clock domain.In file gain.yml
we see that there not any ce_clock domain...
//gain.yml section
clocks:
- name: rfnoc_chdr
freq: "[]"
-
Is it possible that I changed center frequency and gain of USRP from the
Verilog code?
I study API CPP Gnuradio and UHD, In CPP we can change the frequency and
gain of USRP easily ...
But for me there is a question can I change the frequency or gain USRP from
Verilog in an RFNOC block?
Thanks in a
I developed an RFNOC block for USRP x300, When I want to test it in
Gnuradio, the block does not work and I am faced with the below errors ...
How can solve my problem? I mention that it has a critical warning in
synthesis ...This warning is below link:
https://lists.ettus.com/empathy/thread/7HN6J
In the body of an RFNOC block code, I had a for in for and calculation but
when I want to synthesize it I was faced with a clock warning in FPGA. When
I comment on this section this error is disappeared...
So when I used a delay with tag # in some cases warning is removed...
I:Errors:
[00:04:49] C
he code in your RFNoC
> block and gradually uncomment it until you can narrow down what section of
> code is causing Vivado to fail. Hopefully you can narrow down which
> statement is the cause. When you run the build, monitor the memory usage to
> make sure that's not an issue.
>
&
k_correlate.v, then you may need to provide a relative path to
> the file.
>
> Thanks,
>
> Wade
>
> On Mon, Apr 18, 2022 at 4:56 AM sp h wrote:
>
>> Why include a Verilog file not work in the RFNOC block?
>> In Verilog, we can include another file in the source Verilog
Why include a Verilog file not work in the RFNOC block?
In Verilog, we can include another file in the source Verilog file, but
when I did in an RFNOC block I faced errors...
can you any offers?
ERROR: [VRFC 10-3195] cannot open include file 'corrleate.vh'
[rfnoc/rfnoc/fpga/rfnoc_block_correlate/r
Finally, my problem is solved...
NOC_ID value in .sv file and noc_shell file should be same.Otherwise, you
will face erros...
On Sun, Apr 17, 2022 at 10:01 AM sp h wrote:
> Hi, when I changed the name of the Gain block to another name, I want to
> run the test bench and simulated it but
Hi, when I changed the name of the Gain block to another name, I want to
run the test bench and simulated it but I was faced with these errors...
How can solve my problems?
TESTBENCH STARTED: chdr_crossbar_nxn: IP_OPTION = HDL_IP
===
ions on how to run testbenches and load the
> simulation in the Vivado GUI.
>
> My guess is that you have a signal that's not connected correctly, like a
> clock or reset.
>
> Wade
>
> On Tue, Apr 5, 2022 at 12:42 AM sp h wrote:
>
>> When I run the gain examp
When I run the gain example testbench file I am faced with errors.How
can I solve this?
Vivado Simulator does not support tracing of System Verilog Dynamic Type
object.
TESTBENCH STARTED: rfnoc_block_gain_tb
:01 PM sp h wrote:
> But I need to add samples to a buffer. when 4096 sample is received for
> block, do an operation like correlate and convolution, and so on.
>
> Can we use RAM in an RFNOC block that enables us to work with specific
> count samples??
> It is possible?
>
&
Default CHDR_W is 64 for RFNOC blocks when I want to create a custom RFNOC
block, I know that the RFNOC bus block is AXI4, So for accessing samples I
work with some registers in Verilog code ...
m_in_payload_tdata
Details I/Q samples are below...
I/real in [63:32], Q/imaginary in [31:0] (sc32).
What's the max legal value for these parameters in RFNOC blocks?
Can I for an RFNOC block set CHDR_W to 1024?
We know for communication between RFNOC blocks in USRP is used AXI4 stream
bus.
thanks in advance
parameter CHDR_W = 64,
parameter [5:0] MTU = 10
There is an example gain RFNOC block in an old document from UHD but for
the UHD 4 document this example (gain RFNOC block is removed...)
For the new UHD document, NOC shell and pins are changed...anyone gain
RFNOC block for UHD 4 and new documents?
thanks very much
Old doc:
https://kb.ettus.c
When I create an RFNOC block with rfnocmodtool, the block has a default
code...
My question is what to do this default code for RFNOC block? It is a gain
block? It is a buffer block?
What is this code? can anyone guide me...
//
// Copyright 2022 <+YOU OR YOUR COMPANY+>.
//
// This is free
);
> >> z = xcorr(x,y);
> >> Lfft = 2^nextpow2(2*L-1);
> >> z2 = circshift(ifft(fft(x,Lfft).*conj(fft(y,Lfft)),Lfft),L-1);
> >> plot(abs(z-z2(1:2*L-1)))
>
> On Fri, Feb 25, 2022 at 2:30 AM sp h wrote:
>
>> Thanks, I know that I can use FFT but I wa
I am reading RFNOC replay block, end of the Verilog code I faced a debug
code ...
what's mean debug? what does it do?
axi_dma_master #(
.AWIDTH (MEM_ADDR_W),
.DWIDTH (MEM_DATA_W)
) axi_dma_master_i (
//
// AXI4 Memory Mapped Interface to DRAM
//
.aclk (mem_clk),
.areset (mem_rst),
// Write contro
Thanks, I know that I can use FFT but I want to implement Xcorrelate like
xcorr Matlab directly...as an independent RFNOC blocks
On Wed, Feb 23, 2022 at 10:56 AM sp h wrote:
> Thanks, I know that I can use FFT but I want to implement Xcorrelate like
> xcorr matlab directly...as a indep
How can create an RFNOC correlate block for USRP?
This thread is created to share results on searching how we can correlate
RFNOC blocks...
Anyone that had an idea, I'm glad to hear it...
thanks in advance
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Finally found the solution you should manually some files in the icores
folder...For example for x300 go to this path
in UHD/FPGA path:uhd-4.1.0.5/fpga/usrp3/top/x300
copy below files in icores folder..
and change name x300_rfnoc_image_core.yml
to gain_x300_rfnoc_image_core.yml...
for other ser
Thanks, But for another model like B210 and is it not there anyway?
On Fri, Feb 18, 2022 at 5:14 PM Cédric Hannotier
wrote:
> On 18/02/22 12:51, sp h wrote:
> > On Sun, Feb 13, 2022 at 10:51 AM sp h wrote:
> > > How to create the RFNOC block gain for other RFNOC image
Does anyone have not any idea? thanks in advance
On Sun, Feb 13, 2022 at 10:51 AM sp h wrote:
> How to create the RFNOC block gain for other RFNOC image cores...Default
> is for X310, but I want to be x300?
> When I created a new RFNOC module with the below commands, the RFNNOC
> i
How to create the RFNOC block gain for other RFNOC image cores...Default is
for X310, but I want to be x300?
When I created a new RFNOC module with the below commands, the RFNNOC image
core is x310 (my Gnuradio 3.8.1, UHD 4.1.0.5).
$rfnocmodtool newmod transceiver
$cd rfnoc-transceiver
$ rfnocmodto
Finally, I edited the RFNOC image core when I used the default RFNOC image
core x300_rfnoc_image_core.yml, and run below command,
I could successfully open UHD project in GUI vivado. Thanks very much
make X300_HG GUI=1
On Thu, Feb 3, 2022 at 12:13 PM sp h wrote:
> I reformed my previous p
; /home/sp/Documents/rfnoc-tutorial/rfnoc/icores/x310_rfnoc_image_core.yml
>
> Note the include path is the base of the OOT module. Please check that all
> the paths are correct for your setup when trying.
>
> Wade
>
>
> On Tue, Feb 8, 2022 at 1:35 AM sp h wrote:
>
>>
I copied RFNOC gain example from UHD folder, I installed it successfully in
Gnuradio, But for building FPGA
I was faced with these errors.
How can I solve this problem?
Thanks in advance
ERROR: [Synth 8-439] module 'rfnoc_block_gain' not found
[/home/sp/Documents/rfnoc-tutorial/rfnoc/icores/x310_
lk: _device_, srcport: ce,dstblk: gain0, dstport: ce}
>
> However, the gain example in UHD doesn't have a ce clock port, so I assume
> you modified the example to add that clock port. The tool requires all
> clock inputs to be connected.
>
> Wade
>
>
> On Mon,
example for gain that there is in UHD file has errors...
[ERR] 1 unresolved clk domain(s)
[ERR] gain0:ce
[ERR] Please specify the clock(s) to connect
On Sun, Feb 6, 2022 at 7:38 PM sp h wrote:
> I copied the RFNOC example in a folder. for building, I used these
> commands...
> Bui
Yes, I commented on two other clock sections now I built the FPGA
bitstream successfully...
thanks very much
>
x300_with_fft (another copy).yml
Description: application/yaml
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I copied the RFNOC example in a folder. for building, I used these
commands...
Building and Installing an OOT Module
mkdir build
cd build
cmake .. -DUHD_FPGA_DIR=/home/sp/Documents/uhd-4.1.0.5/fpga
make
Building an FPGA Image with OOT Blocks
when I want to build FPGA I used these commands...
make
Hi, In RFNOC image core files I saw that BSP connection?
what's them and what's the difference between ordinary connections and BSP
connections...
thanks in advance
*BSP connections:*
# BSP Connections
- { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport:
ctrlport_radio0 }
- { sr
cause.
>
> You could also share your x300_with_fft.yml contents so others can check
> if they see anything wrong.
>
> Wade
>
> On Fri, Feb 4, 2022 at 11:12 AM sp h wrote:
>
>> No, I built FPGA from Ubuntu 20.04, a physical PC not VM.
>> Ram is enough 12G, In other cases,
build in a VM or on a system with a limited
> amount of RAM?
>
> Jonathon
>
> On Fri, Feb 4, 2022 at 8:44 AM sp h wrote:
>
>> Finally, I found that...
>> In Vivado there is a limit for the number of warnings and errors which
>> are displayed by the tool f
nces-of-the-messages-will-be-disabled-use-the-tcl-command-set_msg_config-to-change-the-current-settings/
https://support.xilinx.com/s/article/53034?language=en_US
On Thu, Feb 3, 2022 at 1:29 PM sp h wrote:
> When I want to build a new image configuration for USRP X300 I was faced
>
When I want to build a new image configuration for USRP X300 I was faced
with [00:12:48] Process terminated. Status: Failure
my new RFNOC core image YAML file, I attached here...
*And when I want to build I used these commands:*
source setupenv.sh --vivado-path=/home/sp/xilinx/Vivado
rfnoc_image
I reformed my previous post, I used this command, so when I want to build
with GUI=1 option I was faced with some errors
make X300_HG GUI=1
but when I want to make without GUI=1 option I have not any eros... how can
solve this problem?
On Mon, Jan 31, 2022 at 2:40 PM sp h wrote:
> when I w
when I want to build an FPGA source for x300 (In Ubuntu 20.04, Gnuradio
3.8.1, uhd-4.1.0.5) I used the below command:
source setupenv.sh --vivado-path=/home/sp/xilinx/Vivado
make X300_HG
But I have been faced with these errors... can any idea for solving this
problem?
[00:00:23] Starting Synthe
When I want to add an FFT block in FPGA image X300, I have errors
'NoneType' object has no attribute 'keys'
I read the below link but I was faced with errors.
https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
I shared the file for x300_core.yml below...
how can I fix the errors...
Tra
I'm sorry for the typo, I reformed it For building Verilog code (&
generating bitstreams ) for the FPGA x300 series which Vivado license for
a developer is necessary?
Webpack license is enough?
Or do we need a full license?
thanks very much
On Mon, Jan 17, 2022 at 10:47 AM sp h wrot
For building Verilog code for FPGA x300 series which license Vivado should
I necessary?
Webpack license is enough?
Or do we need a full license?
thanks very much
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For USRP x310, I had UBX 160 daughterboard, but lately, however, RX works
correctly But transmit mode is not working correctly.
I had no data signal
UBX 160 transmit but only there is a small carrier?
For HackrfOne we had the same problem, we replace RF amplifier IC, now it
works...
b
Which are RFNOC blocks used in UHD Sink/Source(UHD driver) in Gnuradio?
I heard that the UHD sink or UHD source in Gnuradio is composed of some
RFNOC blocks.
When I see the RFNOC blocks, the Radio core is the same UHD but does anyone
know which RFNOC blocks list are used in the UHD driver?
thanks
thanks, Marcus D. Leech, Anyway I sent thanks email with the subject root
message.
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How I can create a correlate RFNOC block, I need a where that buffer radio
samples...
For more information (time-domain) correlate formula please refer to the
below link:
https://en.wikipedia.org/wiki/Cross-correlation
I have a reference signal that should be correlated with the input
signal recei
Hi, for sending my questions, with Gmail I send an email to this
address usrp-users@lists.ettus.com...
The first email is delivered and everything is ok, but the replay email for
me was not delivered...
can anyone help me? why the second and third messages are not delivered?
thanks in advance
_
Hi, I am studying RFNOC blocks for USRP, the file that I am reading is in
the below link...
https://files.ettus.com/app_notes/RFNoC_Specification.pdf
I know Verilog language, so another part I am studying RFNOC blocks Verilog
Code.
However knowing Verilog and RFNoC_Specification is not enough, be
I am studying RFNOC specifications.
https://files.ettus.com/app_notes/RFNoC_Specification.pdf
in the RFNOC software framework, it describes uhd::multi_usrp API. but it
is not clear to me? my question is which is the work of this API? can
anyone explain more about it?
uhd::multi_usrp API An RFNoC
I study RFNOC gain example, in noc_shell_gain.v there are three sections I
want to know whats that means?
what's the difference between three-section? can any explain?
thanks in advance
//-
// Framework Interface
//-
// RFNoC Framework Clocks
input wire rfn
Hi, I am studying gain RFNOC example, there is two Verilog source in the
FPGA-src folder.
(see this link https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0)
*noc_shell_gain.v *& *rfnoc_block_gain.v *
It is described in the referer link,
-
*rfnoc_block_gain.v The top-level synthesizabl
Hi, I started developing RFNOC block in USRP x300, I installed Gnuradio
3.8.1 and UHD 4.0.0
I study below link about how we can create custom RFNOC blocks..
https://kb.ettus.com/Getting_Started_with_RFNoC_Development
*In a section describing a tool...*
The script uhd_image_builder.py is used
I built Gnuradio from the source, Gnuradio version 3.8.1 with UHD 4.1.04 or
UHD 4.0.0(I tested with all UHD versions)
now when I want to install gr-ettus oot in Gnuraadio I am faced with the
below errors...
How can I solve this problem?
Thanks in advance
[ 64%] Swig source ettus_swig.i
Deprecat
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