Re: [Mesa-dev] [PATCH] r600g: Fix UMAD on Cayman

On Tue, Apr 9, 2013 at 3:18 AM, Marek Olšák wrote: > Pushed, thanks. The transform feedback test still doesn't pass, but at least > the hardlocks are gone. Thanks, I have looked into the other issue as well http://lists.freedesktop.org/archives/mesa-dev/2013-March/036941.html The problem arises

Re: [Mesa-dev] [PATCH] i965/vs: Fix DEBUG_SHADER_TIME when VS terminates with 2 URB writes.

On 04/07/2013 06:42 AM, Paul Berry wrote: The call to emit_shader_time_end() before the second URB write was conditioned with "if (eot)", but eot is always false in this code path, so emit_shader_time_end() was never being called for vertex shaders that performed 2 URB writes. --- src/mesa/driv

[Mesa-dev] [Bug 63117] OSMesa Gallium Empty Output

https://bugs.freedesktop.org/show_bug.cgi?id=63117 --- Comment #2 from Brian Paul --- Created attachment 77643 --> https://bugs.freedesktop.org/attachment.cgi?id=77643&action=edit patch for osmesa.c Kevin, can you try this patch? I think the unique thing that vtk is doing is calling OSMesaMak

Re: [Mesa-dev] [PATCH] r600g: Fix UMAD on Cayman

Pushed, thanks. The transform feedback test still doesn't pass, but at least the hardlocks are gone. Marek On Sun, Apr 7, 2013 at 6:29 PM, Martin Andersson wrote: > If there are no objections or comments on this, it would be nice if > someone could commit it. > > //Martin > > On Tue, Apr 2, 20

Re: [Mesa-dev] remove mfeatures.h, take two

On 04/08/2013 11:26 AM, Matt Turner wrote: Ready to commit? Thanks for the reminder. I think it's ready but IIRC only one person besides myself really tested it. I think I could cherry-pick the commits a few at a time to master... -Brian ___ mes

Re: [Mesa-dev] [PATCH 3/3] i965: Prefer Y-tiling on Gen6+.

On Tue, Apr 09, 2013 at 01:17:39AM +0200, Daniel Vetter wrote: > On Mon, Apr 08, 2013 at 07:27:38PM -0700, Kenneth Graunke wrote: > > In the past, we preferred X-tiling for color buffers because our BLT > > code couldn't handle Y-tiling. However, the BLT paths have been largely > > replaced by BLO

Re: [Mesa-dev] [PATCH 3/3] i965: Prefer Y-tiling on Gen6+.

On Mon, Apr 08, 2013 at 07:27:38PM -0700, Kenneth Graunke wrote: > In the past, we preferred X-tiling for color buffers because our BLT > code couldn't handle Y-tiling. However, the BLT paths have been largely > replaced by BLORP on Gen6+, which can handle any kind of tiling. > > We hadn't measur

[Mesa-dev] [PATCH 10/12] glsl: Use vector-insert and vector-extract on elements of gl_ClipDistanceMESA

From: Ian Romanick Variable indexing into vectors using ir_dereference_array is being removed, so this lowering pass has to generate something different. Signed-off-by: Ian Romanick Cc: Paul Berry --- src/glsl/lower_clip_distance.cpp | 36 ++-- 1 file changed,

[Mesa-dev] [PATCH 12/12] glsl: Death to array dereferences of vectors!

From: Ian Romanick Now that all the places that used to generate array derefeneces of vectors have been changed to generate either ir_binop_vector_extract or ir_triop_vector_insert (or both), remove all support for dealing with this deprecated construct. As an added safeguard, modify ir_validate

[Mesa-dev] [PATCH 09/12] glsl: Convert lower_clip_distance_visitor to be an ir_rvalue_visitor

From: Ian Romanick Right now the lower_clip_distance_visitor lowers variable indexing into gl_ClipDistance into variable indexing into both the array gl_ClipDistanceMESA and the vectors of that array. For example, gl_ClipDistance[i] = f; becomes gl_ClipDistanceMESA[i/4][i%4] = f; How

[Mesa-dev] [PATCH 11/12] glsl: Generate correct ir_binop_vector_extract code for out and inout parameters

From: Ian Romanick Like with type conversions on out parameters, some extra copies need to occur to handle these cases. The fundamental problem is that ir_binop_vector_extract is not an lvalue, but out and inout parameters must be lvalues. A previous patch delt with a similar problem in the LHS

[Mesa-dev] [PATCH 08/12] glsl: Generate ir_binop_vector_extract for indexing of vectors

From: Ian Romanick Now ir_dereference_array of a vector will never occur in the RHS of an expression. Signed-off-by: Ian Romanick --- src/glsl/ast_array_index.cpp | 23 +-- 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/src/glsl/ast_array_index.cpp b/src/gls

[Mesa-dev] [PATCH 07/12] glsl: Convert ir_binop_vector_extract in the LHS to ir_triop_vector_insert

From: Ian Romanick The ast_array_index code can't know whether to generate an ir_binop_vector_extract or an ir_triop_vector_insert. Instead it will always generate ir_binop_vector_extract, and the LHS and RHS have to be re-written. Signed-off-by: Ian Romanick --- src/glsl/ast_to_hir.cpp | 24

[Mesa-dev] [PATCH 06/12] glsl: Add lowering pass for ir_triop_vector_insert

From: Ian Romanick This will eventually replace do_vec_index_to_cond_assign. This lowering pass is called in all the places where do_vec_index_to_cond_assign or do_vec_index_to_swizzle is called. Signed-off-by: Ian Romanick --- src/glsl/Makefile.sources | 1 + src/glsl/glsl

[Mesa-dev] [PATCH 04/12] glsl: Lower ir_binop_vector_extract to swizzle

From: Ian Romanick Lower ir_binop_vector_extract with a constant index to a swizzle. This is exactly like ir_dereference_array of a vector with a constant index. Signed-off-by: Ian Romanick --- src/glsl/lower_vec_index_to_swizzle.cpp | 45 + 1 file changed, 45

[Mesa-dev] [PATCH 05/12] glsl: Lower ir_binop_vector_extract to conditional moves

From: Ian Romanick Lower ir_binop_vector_extract with a non-constant index to a series of conditional moves. This is exactly like ir_dereference_array of a vector with a non-constant index. Signed-off-by: Ian Romanick --- src/glsl/lower_vec_index_to_cond_assign.cpp | 45 ++

[Mesa-dev] [PATCH 03/12] glsl: Refactor part of convert_vec_index_to_cond_assign

From: Ian Romanick Use a first function that extract the vector being indexed and the index from the deref. Call the second function that does the real work. Coming patches will add a new ir_expression for variable indexing into a vector. Having the lowering pass split into two functions will

[Mesa-dev] [PATCH 02/12] glsl: Add ir_triop_vector_insert

From: Ian Romanick The new opcode is used to generate a new vector with a single field from the source vector replaced. This will eventually replace ir_dereference_array of vectors in the LHS of assignments. Signed-off-by: Ian Romanick --- src/glsl/ir.cpp | 1 + src/glsl/ir.h

[Mesa-dev] [PATCH 01/12] glsl: Add ir_binop_vector_extract

From: Ian Romanick The new opcode is used to get a single field from a vector. The field index may not be constant. This will eventually replace ir_dereference_array of vectors. This is similar to the extractelement instruction in LLVM IR. http://llvm.org/docs/LangRef.html#extractelement-inst

[Mesa-dev] [PATCH 00/12] Death to array dereferences of vectors!

This series gradually replaces array dereferences of vectors with two expressions. It takes so many patches because changes are needed to the existing lowering passes and because several places in the code generate array dereferences of vectors (e.g., lowering accessed to gl_ClipDistance). There

Re: [Mesa-dev] [PATCH] i965/vs: Fix DEBUG_SHADER_TIME when VS terminates with 2 URB writes.

On 04/08/2013 11:17 AM, Paul Berry wrote: On 8 April 2013 10:37, Ian Romanick mailto:i...@freedesktop.org>> wrote: On 04/07/2013 06:42 AM, Paul Berry wrote: The call to emit_shader_time_end() before the second URB write was conditioned with "if (eot)", but eot is always fals

Re: [Mesa-dev] Mesa 9.1.2? (was Re: Mesa (9.1): 21 new commits)

On 04/05/2013 07:51 PM, Jordan Justen wrote: On Fri, Apr 5, 2013 at 7:03 PM, Ian Romanick wrote: I just cherry picked (almost) all of the marked patches from master that have been out for two weeks or more. There are a couple that I did not pick. With all that out of the way... how does a M

Re: [Mesa-dev] [PATCH 1/2] i965/fs/gen7: Allow reads from MRFs.

Matt Turner writes: > Since they're actually GRFs, we can read from them. > > total instructions in shared programs: 852751 -> 851371 (-0.16%) > instructions in affected programs: 227286 -> 225906 (-0.61%) > (no regressions) I don't see you actually rewriting these GRF reads to be the new MR

Re: [Mesa-dev] [PATCH 2/2] i965/gen7.5: Allow HW primitive restart for all primitive types.

Paul Berry writes: > Gen7.5 (Haswell) hardware supports primitive restart for all primitive > types. It also handles all possible primitive restart indices. > Rather than specialize both can_cut_index_handle_restart_index() and > the switch statement in can_cut_index_handle_prims() for Haswell,

Re: [Mesa-dev] [PATCH] intel: Allocate hiz in intel_renderbuffer_move_to_temp()

On 5 April 2013 16:51, Paul Berry wrote: > On 5 April 2013 15:28, Chad Versace wrote: > >> When moving the renderbuffer to a new miptree, we neglected to allocate >> the hiz buffer for the new miptree. Oops. >> >> Fixes all Piglit depthstencil-render-miplevels tests from crash to pass on >> Sand

Re: [Mesa-dev] [PATCH] intel: Remove the texture_tiling driconf option.

Kenneth Graunke writes: > This option can force textures to be untiled. However, on Gen6+, depth > buffers must be Y-tiled. MSAA buffers also must be Y-tiled. So setting > this option on even a trivial application like glxgears causes assertion > failures in a debug build, and likely GPU hangs

Re: [Mesa-dev] [PATCH 2/2] i965/gen7.5: Allow HW primitive restart for all primitive types.

Series Reviewed-by: Jordan Justen On Mon, Apr 8, 2013 at 11:57 AM, Paul Berry wrote: > Gen7.5 (Haswell) hardware supports primitive restart for all primitive > types. It also handles all possible primitive restart indices. > Rather than specialize both can_cut_index_handle_restart_index() and >

[Mesa-dev] [PATCH 2/2] i965/vs/gen7: Allow reads from MRFs.

Since they're actually GRFs, we can read from them. total instructions in shared programs: 344973 -> 342483 (-0.72%) instructions in affected programs: 245602 -> 243112 (-1.01%) (no regressions) --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 23 +-- 1 files changed, 13 ins

[Mesa-dev] [PATCH 1/2] i965/fs/gen7: Allow reads from MRFs.

Since they're actually GRFs, we can read from them. total instructions in shared programs: 852751 -> 851371 (-0.16%) instructions in affected programs: 227286 -> 225906 (-0.61%) (no regressions) --- src/mesa/drivers/dri/i965/brw_fs.cpp | 22 -- 1 files changed, 12 insert

[Mesa-dev] [PATCH 1/2] i965: Only use brw_draw.c's trim() function when necessary.

brw_draw.c contains a trim() function which modifies the vertex count for quads and quad strips in order to discard dangling vertices. In principle this shouldn't be necessary, since hardware since Gen4 is capable of discarding dangling vertices by itself. However, it's necessary because as a hac

[Mesa-dev] [PATCH 2/2] i965/gen7.5: Allow HW primitive restart for all primitive types.

Gen7.5 (Haswell) hardware supports primitive restart for all primitive types. It also handles all possible primitive restart indices. Rather than specialize both can_cut_index_handle_restart_index() and the switch statement in can_cut_index_handle_prims() for Haswell, just return early if the hard

Re: [Mesa-dev] [PATCH 2/2] mesa: update derived framebuffer state in GetMultisamplefv

Marek Olšák writes: > This makes sure that ctx->DrawBuffer->Visual.samples is up-to-date. Reviewed-by: Eric Anholt pgpTrmcAX8O6l.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mai

Re: [Mesa-dev] [PATCH 1/2] mesa: fix glGet queries depending on derived framebuffer state

Marek Olšák writes: > "ctx->DrawBuffer->Visual" might be invalid if (NewState &_NEW_BUFFERS) != 0. > > NOTE: This is a candidate for stable branches. > --- > src/mesa/main/get_hash_params.py |8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/src/mesa/main/get_has

Re: [Mesa-dev] [PATCH 3/3] i965: Prefer Y-tiling on Gen6+.

Kenneth Graunke writes: > In the past, we preferred X-tiling for color buffers because our BLT > code couldn't handle Y-tiling. However, the BLT paths have been largely > replaced by BLORP on Gen6+, which can handle any kind of tiling. > > We hadn't measured any performance improvement in the pa

[Mesa-dev] [PATCH] intel: Remove the texture_tiling driconf option.

This option can force textures to be untiled. However, on Gen6+, depth buffers must be Y-tiled. MSAA buffers also must be Y-tiled. So setting this option on even a trivial application like glxgears causes assertion failures in a debug build, and likely GPU hangs in a release build. It's just gi

Re: [Mesa-dev] [PATCH 3/3] i965: Prefer Y-tiling on Gen6+.

On Mon, Apr 8, 2013 at 7:27 PM, Kenneth Graunke wrote: > In the past, we preferred X-tiling for color buffers because our BLT > code couldn't handle Y-tiling. However, the BLT paths have been largely > replaced by BLORP on Gen6+, which can handle any kind of tiling. > > We hadn't measured any per

[Mesa-dev] [PATCH] i965: Skip resetting SOL offsets at batch start when contexts are present.

We won't be able to compute them in software with the advent of geometry shaders. Fixes piglit OpenGL 3.1/primitive-restart-xfb flush NOTE: This is a candidate for the 9.1 branch. --- src/mesa/drivers/dri/i965/gen6_sol.c |9 + src/mesa/drivers/dri/i965/gen7_sol_state.c | 18 ++

[Mesa-dev] [PATCH 3/3] i965: Prefer Y-tiling on Gen6+.

In the past, we preferred X-tiling for color buffers because our BLT code couldn't handle Y-tiling. However, the BLT paths have been largely replaced by BLORP on Gen6+, which can handle any kind of tiling. We hadn't measured any performance improvement in the past, but that's probably because com

[Mesa-dev] [PATCH 2/3] i965: Use tiling even for compressed textures.

The code has no rationale for why we would force compressed textures to be untiled, and it appears to work fine. Git archeology indicates that it's been that way dating back to when we first started tiling. Improves performance in GLB27_TRex_C24Z16_FixedTimeStep at 1280x720 by 10.0529% +/- 0.5730

[Mesa-dev] [PATCH 1/3] intel: Refactor selection of miptree tiling

From: Chad Versace This patch (1) extracts from intel_miptree_create() the spaghetti logic that selects the tiling format, (2) rewrites that spaghetti into a lucid form, and (3) moves it to a new function, intel_miptree_choose_tiling(). No behavioral change. As a bonus, it is now evident that th

Re: [Mesa-dev] [PATCH] i965/vs: Fix DEBUG_SHADER_TIME when VS terminates with 2 URB writes.

On 8 April 2013 10:37, Ian Romanick wrote: > On 04/07/2013 06:42 AM, Paul Berry wrote: > >> The call to emit_shader_time_end() before the second URB write was >> conditioned with "if (eot)", but eot is always false in this code >> path, so emit_shader_time_end() was never being called for vertex

Re: [Mesa-dev] [PATCH] i965: Use software primitive restart when transform feedback active.

On 04/06/2013 08:25 PM, Paul Berry wrote: When transform feedback is active, the driver manually counts the number of primitives that run through the pipeline, so that if a batch buffer flush happens, the next batch buffer can pick up transform feedback where the last batch buffer left off. Hard

Re: [Mesa-dev] [PATCH 3/3] glsl/linker: Adapt flat varying handling in preparation for geometry shaders.

On 8 April 2013 10:57, Ian Romanick wrote: > On 04/06/2013 07:49 PM, Paul Berry wrote: > >> When a varying is consumed by transform feedback, but is not used by >> the fragment shader, assign_varying_locations() sets its interpolation >> type to "flat" in order to ensure that lower_packed_varying

Re: [Mesa-dev] [PATCH] i965: Use software primitive restart when transform feedback active.

On 8 April 2013 10:40, Ian Romanick wrote: > On 04/06/2013 08:25 PM, Paul Berry wrote: > >> When transform feedback is active, the driver manually counts the >> number of primitives that run through the pipeline, so that if a batch >> buffer flush happens, the next batch buffer can pick up transf

Re: [Mesa-dev] [PATCH 3/3] glsl/linker: Adapt flat varying handling in preparation for geometry shaders.

On 04/06/2013 07:49 PM, Paul Berry wrote: When a varying is consumed by transform feedback, but is not used by the fragment shader, assign_varying_locations() sets its interpolation type to "flat" in order to ensure that lower_packed_varyings never has to deal with non-flat integral varyings (the

[Mesa-dev] [Bug 56542] [bisected] Piglit gl_select tests crash on exit

https://bugs.freedesktop.org/show_bug.cgi?id=56542 --- Comment #3 from Jerome Glisse --- Dunno if it's a freeglut know bug. They could argue it's not a bug, but really using atexit to do Xorg cleanup is bad. -- You are receiving this mail because: You are the assignee for the bug. _

Re: [Mesa-dev] [PATCH 3/4] st/mesa: add support for ARB_texture_multisample

On 04/06/2013 03:05 AM, Dave Airlie wrote: From: Dave Airlie This adds support to the mesa state tracker for ARB_texture_multisample. hardware doesn't seem to use a different texture instructions, so I don't think we need to create one for TGSI at this time. Thanks to Marek for fixes to sampl

[Mesa-dev] [PATCH 2/2] radeonsi: add support for compressed texture v2

From: Jerome Glisse Most test pass, issue are with border color and swizzle. Based on ircnick patch. v2: Restaged commit hunk Signed-off-by: Jerome Glisse --- src/gallium/drivers/radeonsi/si_state.c | 71 - src/gallium/drivers/radeonsi/sid.h | 7 2

[Mesa-dev] [PATCH 1/2] radeonsi: add 2d tiling support for texture v3

From: Jerome Glisse v2: Remove left over code v3: Restage properly the commit so hunk of first one are not in second one. Signed-off-by: Jerome Glisse --- src/gallium/drivers/radeonsi/r600_texture.c | 11 ++-- src/gallium/drivers/radeonsi/si_state.c | 81 +

Re: [Mesa-dev] [PATCH] i965: Use software primitive restart when transform feedback active.

On 04/06/2013 08:25 PM, Paul Berry wrote: When transform feedback is active, the driver manually counts the number of primitives that run through the pipeline, so that if a batch buffer flush happens, the next batch buffer can pick up transform feedback where the last batch buffer left off. Hard

Re: [Mesa-dev] [PATCH 1/2] mesa: Update comments to match newer specs.

On 04/08/2013 10:29 AM, Matt Turner wrote: Old GL 1.x specs used 'b' but newer specs use 'p'. The line immediately above the second hunk also uses 'p'. Series is Reviewed-by: Ian Romanick --- src/mesa/main/mtypes.h |2 +- src/mesa/main/texobj.c |2 +- 2 files changed, 2 insertio

Re: [Mesa-dev] [PATCH] i965/vs: Fix DEBUG_SHADER_TIME when VS terminates with 2 URB writes.

On 04/07/2013 06:42 AM, Paul Berry wrote: The call to emit_shader_time_end() before the second URB write was conditioned with "if (eot)", but eot is always false in this code path, so emit_shader_time_end() was never being called for vertex shaders that performed 2 URB writes. I had to look at

Re: [Mesa-dev] [PATCH] i965: Use software primitive restart when transform feedback active.

Reviewed-by: Jordan Justen On Sat, Apr 6, 2013 at 8:25 PM, Paul Berry wrote: > When transform feedback is active, the driver manually counts the > number of primitives that run through the pipeline, so that if a batch > buffer flush happens, the next batch buffer can pick up transform > feedback

[Mesa-dev] [PATCH 2/2] mesa: Use MIN3 instead of two MIN2s.

--- src/mesa/main/texobj.c |9 + 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c index d0fcb12..28b8130 100644 --- a/src/mesa/main/texobj.c +++ b/src/mesa/main/texobj.c @@ -548,10 +548,11 @@ _mesa_test_texobj_completeness(

[Mesa-dev] [PATCH 1/2] mesa: Update comments to match newer specs.

Old GL 1.x specs used 'b' but newer specs use 'p'. The line immediately above the second hunk also uses 'p'. --- src/mesa/main/mtypes.h |2 +- src/mesa/main/texobj.c |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index

Re: [Mesa-dev] remove mfeatures.h, take two

Ready to commit? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] glsl: Fix ir_print_visitor's handling of interpolation qualifiers.

On 04/06/2013 07:20 PM, Paul Berry wrote: This patch updates the interp[] array to match the enum glsl_interp_qualifier. Can we use STATIC_ASSERT to make sure these arrays are at least the correct size? --- src/glsl/ir_print_visitor.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(

Re: [Mesa-dev] [PATCH 2/2] radeonsi: add support for compressed texture

On 04/08/2013 02:03 PM, Marek Olšák wrote: On Mon, Apr 8, 2013 at 11:29 AM, Michel Dänzer wrote: On Fre, 2013-04-05 at 17:36 -0400, j.gli...@gmail.com wrote: From: Jerome Glisse Most test pass, issue are with border color and swizzle. FWIW, those issues are there with non-compressed forma

Re: [Mesa-dev] [PATCH 12/17] i965/vs: Generalize data structures pointed to by vec4_generator.

Paul Berry writes: > This patch removes the following field from vec4_generator, since it > is not used: > > - struct brw_vs_compile *c > > And changes the following field: > > - struct gl_vertex_program *vp => struct gl_program *glprog Same comment about prog/shader_prog as a naming solution.

Re: [Mesa-dev] [PATCH 06/17] i965/vs: split brw_vs_prog_data into generic and VS-specific parts.

Paul Berry writes: > -/* Note: brw_vs_prog_data_compare() must be updated when adding fields to > this > - * struct! > + > +/* Note: brw_vec4_prog_data_compare() must be updated when adding fields to > + * this struct! > */ > -struct brw_vs_prog_data { > +struct brw_vec4_prog_data { > struc

Re: [Mesa-dev] [PATCH 02/17] i965: Generalize computation of VUE map in preparation for GS.

Paul Berry writes: > This patch modifies the arguments to brw_compute_vue_map() so that > they no longer bake in the assumption that we are generating a VUE map > for vertex shader outputs. It also makes the function non-static so > that we can re-use it for geometry shader outputs. Reviewed-by

Re: [Mesa-dev] [PATCH 11/17] i965/vs: move VS-specific data members to vs_vec4_visitor.

Paul Berry writes: > This patch moves the following data structures from vec4_visitor to > vec4_vs_visitor, since they contain VS-specific data: > > - struct brw_vs_compile *c > - struct brw_vs_prog_data *prog_data > - src_reg *vp_temp_regs > - src_reg vp_addr_reg > > Since brw_vs_compile and brw

Re: [Mesa-dev] [PATCH 1/5] i965: Remove the BRW_NEW_INPUT_DIMENSIONS flag.

Kenneth Graunke writes: > When I removed the proj_attrib_mask optimization, I also removed the > last consumer of this bit without realizing it. > > Since nobody uses it, there's no point in flagging it. Series is: Reviewed-by: Eric Anholt pgpk5NUvBfZ1J.pgp Description: PGP signature ___

Re: [Mesa-dev] [PATCH 01/17] i965/vs: Make type of vec4_visitor::vp more generic.

Paul Berry writes: > The vec4_visitor functions don't use any VS specific data from > vec4_visitor::vp. So rename it to just "p" and change its type from > struct gl_vertex_program * to struct gl_program *. This will allow > the code to be re-used for geometry shaders. In many other places in

Re: [Mesa-dev] [PATCH] clover: Fix linkage of libOpenCL

On Thu, Apr 04, 2013 at 11:26:45PM +0200, Niels Ole Salscheider wrote: > Clover needs the irreader component of llvm > > v2: Check for irreader component > irreader is only available with LLVM 3.3 >= 177971 > > Signed-off-by: Niels Ole Salscheider I've pushed this, thanks. btw, I also pushed y

Re: [Mesa-dev] [PATCH] st/mesa: fix levels in initial texture creation

On 04/06/2013 10:31 PM, Dave Airlie wrote: From: Dave Airlie calim pointed out we were getting mipmap levels for array multisamples, this didn't make sense. So then I noticed this function takes last_level so we are passing in a too high value here. I think this should fix the case he was seein

Re: [Mesa-dev] [PATCH] tgsi: Ensure struct tgsi_ind_register field Index is initialized.

On 04/06/2013 10:33 PM, Vinson Lee wrote: Fixes uninitialized scalar variable defect reported by Coverity. Signed-off-by: Vinson Lee --- src/gallium/auxiliary/tgsi/tgsi_build.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.c b/src/gallium/auxiliary

[Mesa-dev] [Bug 63269] New: explicitly symlinking libraries without libtool breaks OpenBSD build

https://bugs.freedesktop.org/show_bug.cgi?id=63269 Priority: medium Bug ID: 63269 Assignee: mesa-dev@lists.freedesktop.org Summary: explicitly symlinking libraries without libtool breaks OpenBSD build Severity: normal Cla

Re: [Mesa-dev] [PATCH 2/2] radeonsi: add support for compressed texture

Christoph, You're talking about something entirely different. I was trying to explain that a correct swizzled border color is *impossible* on r600 and later chipsets. I think your hardware is actually good and can do swizzled border color with a little bit of driver work you refuse to do. :) You h

Re: [Mesa-dev] [PATCH 2/2] radeonsi: add support for compressed texture

On 08.04.2013 12:03, Marek Olšák wrote: > On Mon, Apr 8, 2013 at 11:29 AM, Michel Dänzer > wrote: > > On Fre, 2013-04-05 at 17:36 -0400, j.gli...@gmail.com > wrote: > > From: Jerome Glisse mailto:jgli...@redhat.com>> > > >

Re: [Mesa-dev] [PATCH 2/2] radeonsi: add support for compressed texture

On Mon, Apr 8, 2013 at 11:29 AM, Michel Dänzer wrote: > On Fre, 2013-04-05 at 17:36 -0400, j.gli...@gmail.com wrote: > > From: Jerome Glisse > > > > Most test pass, issue are with border color and swizzle. > > FWIW, those issues are there with non-compressed formats as well. I'm > afraid we migh

Re: [Mesa-dev] [PATCH 2/2] radeonsi: add support for compressed texture

On Fre, 2013-04-05 at 17:36 -0400, j.gli...@gmail.com wrote: > From: Jerome Glisse > > Most test pass, issue are with border color and swizzle. FWIW, those issues are there with non-compressed formats as well. I'm afraid we might need to change the hardware border colour depending on the swizzl

Re: [Mesa-dev] [PATCH 4/4] radeonsi: Handle new format for configuration values emitted by the LLVM backend

On Fre, 2013-04-05 at 14:54 -0400, Tom Stellard wrote: > From: Tom Stellard > > Instead of emitting configuration values (e.g. number of gprs used) in a > predefined order, the LLVM backend now emits these values in > register/value pairs. The first dword contains the register address and > the

Re: [Mesa-dev] [PATCH 00/17] i965/vs: Generalize VS compiler back-end in preparation for GS.

Reviewed-by: Jordan Justen On Sun, Apr 7, 2013 at 3:53 PM, Paul Berry wrote: > This patch series lays the groundwork for the i965 geometry shader > back-end by separating the functions and data structures which are > specific to vertex shaders from those that can also be used to compile > geomet