On Tue, Apr 09, 2013 at 01:17:39AM +0200, Daniel Vetter wrote: > On Mon, Apr 08, 2013 at 07:27:38PM -0700, Kenneth Graunke wrote: > > In the past, we preferred X-tiling for color buffers because our BLT > > code couldn't handle Y-tiling. However, the BLT paths have been largely > > replaced by BLORP on Gen6+, which can handle any kind of tiling. > > > > We hadn't measured any performance improvement in the past, but that's > > probably because compressed textures were all uncompressed anyway. > > Long ago when I've drawn diagramms showing which pixels lay in which > cachelines for enabling tiling on i915g I've figured that at least for the > 4x4 block compressed layouts with 128bits per block X and Y tiling should > result in about equally optimal layouts (just cachelines stack > differently): X-tiled actually gives you an 8x8 grid of 4x4 blocks, so > I've figured that'll be better for tlb efficiency.
Blergh, can't do math, should be 8x32 or 32x8 grids of 4x4 blocks in a tile. So on a quick look x/y-tiled are about equally nicely laid out. I've mixed up the 8x8 with the cacheline pattern of y-tiled, where each cacheline is a 4x4 pixel block (at least for 32bit-per-pixel stuff). -Daniel > Anyway I've never done real benchmarks, I'm just curious that you blame > all the speedup here on compressed textures and wonder a bit what that'd > look like when (some) of the compressed layouts would keep on using x > tiled. But it's gettin a bit late here ;-) > -Daniel > > > > > Improves performance in GLB27_TRex_C24Z16_FixedTime by 7.69231%. > > > > Signed-off-by: Kenneth Graunke <kenn...@whitecape.org> > > --- > > src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c > > b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c > > index 8dd04be..6a9f08c 100644 > > --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c > > +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c > > @@ -344,7 +344,7 @@ intel_miptree_choose_tiling(struct intel_context *intel, > > return I915_TILING_Y; > > > > if (width0 >= 64) > > - return I915_TILING_X; > > + return intel->gen >= 6 ? I915_TILING_Y : I915_TILING_X; > > > > return I915_TILING_NONE; > > } > > -- > > 1.8.1.1 > > > > _______________________________________________ > > mesa-dev mailing list > > mesa-dev@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/mesa-dev > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
