Hi all,
We observe different behaviour using the E320 radio with the UHD:
USRP_SOURCE block and the RFNoC Radio block with a low sampling rate.
We are attempting to set the sampling rate to 25 kHz for both blocks. In
the UHD block, we achieve this by configuring the sampling rate to 25 kHz.
Simila
Hi all,
We are using UHD 4.0 with RFNoC and GNURadio in an E320 device.
We've always used the RF-A antenna channel without problems, but now we are
trying to use the RF-B channel and are unsure how to configure the rfnoc
radio block to do that.
We have also tried to put both channels receiving an
Hi,
I'm trying to run a gnuradio graph with Rx to Tx rfnoc radios in uhd 4.6
new installation, but I'm having the following error: RuntimeError:
RfnocError: Adding edge without disabling is_forward_edge will lead to
unresolvable graph!
In UHD 4.0, I used to install gr-ettus (commit:
865f7d9fbe4fa
Hi Martin,
I have figured it out when you write the path. There was a misspelling,
"gr_ettus" instead of "gr-ettus". Now, I can build the image, thank you!
Kind Regards,
El jue, 18 jul 2024 a las 18:06, Martin Braun ()
escribió:
>
> On Thu, Jul 18, 2024 at 3:06 PM M
hings in
> the way the image core YAML files are constructed.
>
> --M
>
> On Thu, Jul 18, 2024 at 11:32 AM Maria Muñoz wrote:
>
>> Hi Martin,
>>
>> I had another issue once I resolved the YML problem. I start the
>> synthesis with this command:
>>
&g
o other version installed.
>
> --M
>
> On Wed, Jul 17, 2024 at 12:22 PM Maria Muñoz wrote:
>
>> Hi Martin,
>> .
>> Thanks for your answer. I will do the workaround.
>> By the way, I'm using Ubuntu 20.04.
>>
>> Kind Regards,
>>
>>
, we will need to fix this ASAP (note to myself)
>>
>>
>> Can you provide some info on your system (OS, distribution, etc.)? Many
>> thanks,
>>
>> Martin
>>
>> On Wed, Jul 17, 2024 at 11:05 AM Maria Muñoz wrote:
>>
>>> Hi all,
>>&g
Hi all,
I'm trying to use the UHD 4.6 version with RFNoC to build an image for the
x440 USRP device. I used UHD 4.0 for USRP E320 without a problem, but now I
have an issue with the YML files for the X440 image building.
I have installed UHD 4.6, GNURadio 3.8, and gr-ettus (to have the
rfnocmodtoo
Hi all,
I have a problem trying to power up the USRP E320.
When I push the power button, the power led doesn't light up and the eth
leds blink for a few seconds and then shut down. This is not the first time
this has happened to an E320 device (for the other cases I recovered them
by pushing the
xi_intercon_4x64_256_bd
>
> https://github.com/EttusResearch/uhddev/blob/UHD-4.0/fpga/usrp3/top/e320/e320_core.v#L610
>
> Wade
>
> On Thu, Oct 20, 2022 at 5:27 AM Maria Muñoz wrote:
>
>> Hi all,
>>
>> I am using UHD 4.0 in an E320 USRP.
>> I would like to
Hi all,
I am using UHD 4.0 in an E320 USRP.
I would like to use the axi_ram_fifo block to communicate with the DMA, but
I have some doubts about it.
I notice that the maximum width I can test is 64, if I try 128 or 256 it
fails. The io_signatures.yml file has this line:
Axi_ram:
Type: axi4_mm_4x6
Hi all,
I am using USRP E320. I was wondering if the RFNoC framework allows some
kind of bitstream protection/authentication like the bitstream encryption
option that offers vivado (
https://docs.xilinx.com/v/u/en-US/xapp1239-fpga-bitstream-encryption).
In that case, how can I load the encrypted b
e way you expect.
>
> Wade
>
> On Tue, Jun 14, 2022 at 12:27 PM Maria Muñoz wrote:
>
>> Hi again Wade,
>>
>> After making some synthesis with and without the clock wizard ip, I have
>> observed that there is higher timing paths for those which use the ip
>&
Vivado, or
> just copy/paste the generated code you need and paste it into your design.
>
> Wade
>
> On Mon, Jun 6, 2022 at 9:40 AM Maria Muñoz wrote:
>
>> Hi all,
>>
>> Thanks for your answers.
>>
>> Wade, you are correct, I am trying to instance a
>> 3)When I created a custom RFNOC block, Testbench and generate bitstream
>> is ok but for working RFNOC block in GNURadio I faced with error section 2.
>> Generate OO in Gnuradio
>>
>>
>> [image: Screenshot from 2022-06-06 12-34-22.png]
>>
>>
I am able
>> to copy the rfnoc-example folder to an OOT location and build it and I know
>> it has both OOT and in-tree IP options. In the past I have successfully
>> run the 'make ' and also built an image such as "make
>> ". But, outside of that, I don&
core. Is there something else I have to do?
Kind regards,
Maria
El mié, 1 jun 2022 a las 17:48, Rob Kossler () escribió:
> Hi Maria,
> The rfnoc-example folder within the UHD tree shows an example of how to
> add an out-of-tree IP block. Did you look at this yet?
> Rob
>
> O
he RFNoC framework.So in
> the YAML it is called "rfnoc_chdr".
>
> Wade
>
> On Wed, Jun 1, 2022 at 3:41 AM Maria Muñoz wrote:
>
>> Hi Wade,
>>
>> Thanks for the answer. So "rfnoc_chdr" in the yml file is "bus_clk"?
>> In the re
Hi all,
I'm trying to synthesize a design that includes a vivado ip core inside.
Normally, I add my .vhd/.v source files to the Makefile.srcs inside my
block like this:
RFNOC_OOT_SRCS += $(addprefix $(dir $(abspath $(lastword
$(MAKEFILE_LIST, \
source1.vhd \
source2.v \
source3.v \
)
But add
t; to "rfnoc_chdr" in the line for your block in the clk_domains section.
> If that doesn't work, share your YML file and maybe someone can spot the
> problem.
>
> Wade
>
> On Tue, May 31, 2022 at 3:47 AM Maria Muñoz wrote:
>
>> Hi all,
>>
>> I have gener
Hi all,
I have generated a custom RFNoC block with rfnocmodtool to be implemented
on X310.
I am using UHD 4.0. toolchain to synthesize it, but I cannot meet timing
with the clock selected (in /icores/yml file, I have select "ce" as the clk
source for my block).
I see that "ce" clock for X310 is 21
).
I still haven't found a solution for GNURadio complaining about the
"previously registered RFNoC block" but seems another issue not related to
this one.
Thanks again for your help.
Kind Regards,
Maria
El lun, 21 feb 2022 a las 18:44, Maria Muñoz ()
escribió:
> Ok Rob, I wil
m the DDC
> controller instead of the rx_streamer.
>
> Rob
>
>
>
> On Mon, Feb 21, 2022 at 11:52 AM Maria Muñoz wrote:
>
>> This is my output for gnuradio:
>>
>> *REGISTRY] WARNING: Attempting to overwrite previously registered RFNoC
>> block w
modification?
>
> By the way, each FPGA block (such as DDC) has a corresponding UHD block
> controller (running on the host side). So, it is possible to run
> issue_stream_cmd from the DDC controller rather than the rx_streamer. I
> just don't remember how exactly to do tha
folder. Note that this example
>does very little (empty constructor). At the bottom is a string
>identifying the block which is the string that will be shown with
>uhd_usrp_probe if UHD is using your block controller.
>
> Let me know if this is the issue. Once you
ller is not
>> forwarding actions, the Radio controller never gets the action and thus
>> never starts the streaming. One way you can verify this is if you are able
>> to call issue_stream_cmd() from the DDC controller rather than the
>> rx_streamer. This should cause your strea
Hi all,
I'm using a USRP E320 with UHD 4.0 and GNURadio 3.8 for receiving
samples through an RX RFNoC Radio block and performing some processing in a
custom RFNoC block.
I have created my block using rfnocmodtool, modifying the Verilog and yml
files for my custom block. I left the cpp and hpp file
Hi all,
I try to transmit a signal through an RFNoC Radio TX block in a USRP E320.
I am using UHD 4.0 and GNURadio 3.8.
My flowgraph in Gnuradio is something like this:
Host block => RFNoC tx Streamer => RFNoC custom block => RFNoC DUC => RFNoC
tx radio
When I test this graph with "number of por
onsole only, or perhaps you could try running just your simulation in the
> GUI of a newer version of Vivado.
>
> Thanks,
>
> Wade
>
> On Wed, Jan 12, 2022 at 4:08 AM Maria Muñoz wrote:
>
>> Hi all,
>>
>> I am using USRP E320 with UHD 4.0, GNURadio 3.8 a
Hi all,
I am using USRP E320 with UHD 4.0, GNURadio 3.8 and gr-ettus master
versions.
I have made a custom RFNoC block using rfnocmodtool. Since the
skeleton that this tool creates only has 1 input and 1 output, I have
modified the yml block generated to have 2 inputs and 2 outputs and then
I've
o the problem? I have also tried to change the ID of
the block but this still doesn't work. Any new ideas on your side Paul?
Someone can help us?
Kind Regards,
Maria
El lun, 31 may 2021 a las 9:09, Maria Muñoz () escribió:
> Oh! I hope someone can tell us what might be wrong with the blo
eides ()
escribió:
> I second this. I’m having almost the exact same issue with split stream.
> Mine returns attribute error no module found, but as shown in Maria’s
> post, it’s displayed fine in grc and the image.
>
>
>
> On May 28, 2021, at 04:45, Maria Muñoz wrote:
>
>
>
Hi all,
I have this warning trying to load an image on the USRP E320. ¿What does it
mean? ¿How can I solve it?
Kind Regards,
Maria.
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Hi Paolo,
Ok! I'll check on the E320 device. Thanks again.
Kind Regards,
Maria.
El jue, 13 may 2021 a las 12:12, Maria Muñoz ()
escribió:
> Hi Paolo,
>
> Thanks for the quick answer.
>
> I'm sorry I forgot to say that I'm using USRP E320, but I can apply w
mean that my throughput would be also affected by
those clocks too? Maybe the maximum theoretical throughput could be
calculated using the lowest clock of them(which would be bus_clk in the
X300 case)?
Kind Regards,
Maria
El jue, 13 may 2021 a las 10:28, Maria Muñoz ()
escribió:
> Hi all,
&
Hi all,
I'm trying to size/calculate the throughput between RFNoC blocks from the
FPGA side (not between arm/host pc and RFNoC block, which I think is the
one the interface measure when performing uhd_usrp_probe). Is there a
process or an existing tool to measure this throughput?
Kind Regards,
M
Hi all,
I'm trying to load the Aurora default FPGA image in USRP E320 but when I
make uhd_usrp_probe I'm getting the following error:
[ERROR] [RFNOC::GRAPH] Caught exception while initializing graph:
RfnocError: Specified destination address is unreachable
I am using UHD 4.0 and 2 connections, o
Hi all,
I'm having similar issues with the cross-compilation of UHD that are posted
in this post:
http://ettus.80997.x6.nabble.com/USRP-users-Cross-Compile-Issues-with-E320-tt15748.html
I have installed the last E320 SDK using "uhd_images_downloader -t e320 -t
sdk -i ~/home/rfnoc/src" as suggeste
> > I also have UHD 4.0 and GNURadio 3.8 (installed by source).
> >
> > The steps I take are these:
> >
> > * First, I change the ad9361_device.cpp that is in uhd repository in
> > //uhd/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp,
> >
n script for the GRC flow graph and
move the "set_agc" command after the "set_rate" one.
- Finally, I run the python.
I can't see my waveform between the values I set. Is there something wrong
with those steps? Did you do anything else?
King Regards,
Maria
El ma
ely kept
> between -2 dBFS and -4 dBFS.
>
> Attached is a picture of the flow-graph I used for testing. Maybe you
> could also start by testing with a sine wave to verifying that your
> values get applied properly.
>
> Cheers,
> Julian
>
> On 3/22/21 6:21 PM, Maria Muñ
m to stay in the same limits as the default configuration).
Am I missing any other step that I have to done to configure these
parameters?
Kind Regards,
Maria
El vie, 12 mar 2021 a las 10:04, Maria Muñoz ()
escribió:
> Ok Julian, I will check the tree node and try to modify the properties.
&
implemented as far as I know.
> Which mode you want ("slow" / "fast") depends on the signal you want to
> receive. For burst-mode digital signals you might want to switch to the
> "fast" mode.
> However, I think this is only possible by directly writing
> to t
et_rx_agc(enable,0)" isn't it?
>
> Exactly! Take a look at [1] for the correct syntax.
>
> [1]
>
> https://github.com/EttusResearch/gr-ettus/blob/1038c4ce5135a2803b53554fc4971fe3de747d9a/include/ettus/rfnoc_rx_radio.h#L97
>
> Let me know if that worked out for you.
>
>
re was a bug in an earlier version of gr-uhd
> (somewhere in 3.7) that made it difficult to turn on the AGC using GRC.
> That particular one is fixed in gr-uhd. Not sure about gr-ettus, though.
>
> Maybe try using set_rx_agc() manually in you flow-graph (*.py) and see
> if that helps
Hi all,
I was wondering if it is possible to enable AGC from the RFNoC radio block
in GNURadio. I use UHD 4.0 version and GNURadio 3.8 with gr-ettus.
I see that the RFNoC Rx radio block has an enable/disable/default AGC
option in the GNURadio block which I assume calls the UHD function
"set_rx_ag
>
> Also, as you've noticed, the generated yaml file has the wrong interface,
> "fpga_iface: axis_data" should be "fpga_iface: axis_pyld_ctxt". That is a
> known issue that is in the pipeline to be fixed.
>
> Jonathon
>
> On Wed, Jan 20, 2021 at 8:18 AM M
Hi all,
Is it possible to automatically create an rfnoc_block schema with, for
example, 2 inputs and 2 outputs payload stream packets as in the addsub
blockdata using rfnocmodtool?
I can generate it using rfnoc_create_verilog.py through a block.yml file
following the steps in :
https://kb.ettus.co
Hi all,
I have tried to install a custom OOT RFNoC block created using the
rfnocmodtool.
I've successfully created a module with my custom block, modifying the
verilog file created by the tool (
*rfnoc-test/rfnoc/fpga/rfnoc_block_myblock/rfnoc_block_myblock.v*) to
include the top level of my code
he port name is different in this
> case. I was recently working on fixing that so that, hopefully, you won't
> have to update the port name for changes like this in the future.
>
> Thanks,
>
> Wade
>
> On Wed, Nov 25, 2020 at 2:42 AM Maria Muñoz wrote:
>
>
o what I want to do. Is there any
documentation about this part of the yaml file? I have read the "Getting
started with RFNoC in UHD 4.0" (
https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0) but I can't see
what makes this part of the file.
Kind Regards,
Maria
El mié, 25
-- Forwarded message -
De: Maria Muñoz
Date: lun, 23 nov 2020 a las 10:05
Subject: Re: [USRP-users] FPGA RFNoC Radio block with only one channel
To: Wade Fife
Hi Wade,
Thanks for your answer that helps me a lot.
I have migrated to UHD 4.0 as you suggested so just a few
Hi everyone,
I'm using an USRP E320 using the RFNoC image to implement a code that
requires too much FPGA resources. I only need to use one of the channels of
the USRP so I was wondering if it could be possible to eliminate the logic
associated with the other channel to save resources on the FPGA
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