Hi all, I am using USRP E320 with UHD 4.0, GNURadio 3.8 and gr-ettus master versions.
I have made a custom RFNoC block using rfnocmodtool. Since the skeleton that this tool creates only has 1 input and 1 output, I have modified the yml block generated to have 2 inputs and 2 outputs and then I've run the rfnoc_create_verilog.py script inside the block folder. This creates the noc shell and block Verilog files with 2 inputs and 2 outputs. When I modify the block Verilog file with my code and try to test it with the interface tb to send and receive packages, I have timeout. I have simulated my code in Vivado and works as expected, so I think the problem comes with the interface between my block and rfnoc. I also try to bypass my code (axis inputs to axis output) and still have a timeout issue. I try to open the simulation in GUI mode, but Vivado crashes. I test the gain block tutorial created with rfnocmodtool (1 input and 1 output) and it works fine. So I have several questions: Is it possible to have custom block with 2in/2out (or several inputs/outputs)? What is the best way to do it? Is there a way to open simulation with the rfnoc framework in GUI mode directly? (I have modified the simulation.tcl with -g option created once I run make tb) Kind Regards, Maria
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