Hi everyone, I'm using an USRP E320 using the RFNoC image to implement a code that requires too much FPGA resources. I only need to use one of the channels of the USRP so I was wondering if it could be possible to eliminate the logic associated with the other channel to save resources on the FPGA and if there is a 'safe' way to do that. I mean I have seen on the verilog source code, that there is a parameter 'NUM_CHANNELS_PER_RADIO' (e320.v on fpga repository) which configures the channels of the radio, but what happens with the tx_i1, tx_q1, rx_i1 and rx_1q signals that goes to the LVDS interface with the ADC? Can they be left unconnected? Is there another parameter that I must change to use only one channel and eliminate the 'extra' logic?
Kind Regards, Maria
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