Hi Wade, Thanks for the help.
I have reduced the number of input/outputs of my block to 1 in and 1 out, and that way there's no timeout, but some unknown X values in s_rfnoc_chdr_tdata/m_rfnoc_chdr_tdata ports. I manage to open the Vivado simulation in a newer version and as you said it works. So I will check there and compare with the blocks that you mention. Thanks again, Maria El mié, 12 ene 2022 a las 16:36, Wade Fife (<wade.f...@ettus.com>) escribió: > Hi Maria, > > The addsub block is an example with two inputs and two outputs. > > > https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_addsub/rfnoc_block_addsub.v > > https://github.com/EttusResearch/uhd/blob/master/host/include/uhd/rfnoc/blocks/addsub.yml > > Moving Average is an example with a configurable number of ports. The > NUM_PORTS parameter is used to set the number of input ports, which in this > case is always the same as the number of output ports. Several of the > blocks are set up like this one. > > > https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_moving_avg/rfnoc_block_moving_avg.v > > https://github.com/EttusResearch/uhd/blob/master/host/include/uhd/rfnoc/blocks/moving_avg.yml > > To run the simulation in the GUI, add GUI=1 to the make command. > > make xsim GUI=1 > > You can find more information about running simulations in the manual. > > https://files.ettus.com/manual/md_usrp3_sim_running_testbenches.html > > Unfortunately, the Vivado crashing is a known issue that we have reported > to Xilinx. It should be resolved when we upgrade Vivado versions. In the > mean time you could use ModelSim if you have access, or run xsim from the > console only, or perhaps you could try running just your simulation in the > GUI of a newer version of Vivado. > > Thanks, > > Wade > > On Wed, Jan 12, 2022 at 4:08 AM Maria Muñoz <mamuk...@gmail.com> wrote: > >> Hi all, >> >> I am using USRP E320 with UHD 4.0, GNURadio 3.8 and gr-ettus master >> versions. >> >> I have made a custom RFNoC block using rfnocmodtool. Since the >> skeleton that this tool creates only has 1 input and 1 output, I have >> modified the yml block generated to have 2 inputs and 2 outputs and then >> I've run the rfnoc_create_verilog.py script inside the block folder. This >> creates the noc shell and block Verilog files with 2 inputs and 2 outputs. >> When I modify the block Verilog file with my code and try to test it with >> the interface tb to send and receive packages, I have timeout. >> I have simulated my code in Vivado and works as expected, so I think the >> problem comes with the interface between my block and rfnoc. I also try to >> bypass my code (axis inputs to axis output) and still have a timeout >> issue. I try to open the simulation in GUI mode, but Vivado crashes. I >> test the gain block tutorial created with rfnocmodtool (1 input and 1 >> output) and it works fine. >> >> So I have several questions: >> >> Is it possible to have custom block with 2in/2out (or several >> inputs/outputs)? What is the best way to do it? >> Is there a way to open simulation with the rfnoc framework in GUI mode >> directly? (I have modified the simulation.tcl with -g option created once I >> run make tb) >> >> Kind Regards, >> >> Maria >> >> _______________________________________________ >> USRP-users mailing list -- usrp-users@lists.ettus.com >> To unsubscribe send an email to usrp-users-le...@lists.ettus.com >> >
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