Hi Julian,
Thanks for the quick answer.
I think you might be right about the possible bug turning on the AGC from
GRC. I have checked the flow graph generated and there's no set_rx_agc
enable option (I checked the c++ definition block where this option did
appear but I hadn't look at the python generated).
The lines related to the radio in my flowgraph are these:
*self.ettus_rfnoc_rx_radio_0 = ettus.rfnoc_rx_radio(
self.rfnoc_graph, uhd.device_addr(''), -1,
-1) self.ettus_rfnoc_rx_radio_0.set_rate(samp_rate)
self.ettus_rfnoc_rx_radio_0.set_antenna('RX2', 0)
self.ettus_rfnoc_rx_radio_0.set_frequency(cf, 0)
self.ettus_rfnoc_rx_radio_0.set_gain(gain, 0)
self.ettus_rfnoc_rx_radio_0.set_bandwidth(samp_rate, 0)
self.ettus_rfnoc_rx_radio_0.set_dc_offset(True, 0)
self.ettus_rfnoc_rx_radio_0.set_iq_balance(True, 0)*
So, if I understand correctly, I have to put there also something like
"self.ettus_rfnoc_rx_radio_0.set_rx_agc(enable,0)" isn't it?
Kind Regards,
Maria
El mié, 10 mar 2021 a las 9:16, Julian Arnold (<jul...@elitecoding.org>)
escribió:
> Maria,
>
> I might not be the right person to answer this, as my experience with
> UHD 4.0 is relatively limited at the moment.
>
> However, I cant tell you that the AGC on B2x0 devices is controlled via
> software (using set_rx_agc()). There is no need to directly modify the
> state of any pins of the FPGA.
>
> I vaguely remember that there was a bug in an earlier version of gr-uhd
> (somewhere in 3.7) that made it difficult to turn on the AGC using GRC.
> That particular one is fixed in gr-uhd. Not sure about gr-ettus, though.
>
> Maybe try using set_rx_agc() manually in you flow-graph (*.py) and see
> if that helps.
>
> Cheers,
> Julian
>
> On 3/9/21 5:11 PM, Maria Muñoz via USRP-users wrote:
> > Hi all,
> >
> > I was wondering if it is possible to enable AGC from the RFNoC radio
> > block in GNURadio. I use UHD 4.0 version and GNURadio 3.8 with gr-ettus.
> >
> > I see that the RFNoC Rx radio block has an enable/disable/default AGC
> > option in the GNURadio block which I assume calls the UHD function
> > "set_rx_agc"
> > (
> https://files.ettus.com/manual/classuhd_1_1usrp_1_1multi__usrp.html#abdab1f6c3775a9071b15c9805f866486
> )
> >
> > I have also checked on the FPGA side that there is a pin from FPGA to
> > AD9361 called XCVR_ENA_AGC which is set always to 1 on the top level of
> > the FPGA image (see attached file "e320.v", line 872). This pin,
> > according to
> >
> https://www.analog.com/media/en/technical-documentation/data-sheets/AD9361.pdf
> > is the "Manual Control Input for Automatic Gain Control (AGC)".
> > Must be this pin set to 0 to have AGC working?
> > If not, how can I get AGC working? I've made some tests
> > enabling/disabling this option but I do not see any changes between the
> > waveforms received.
> >
> > Any help would be appreciated.
> >
> > Kind Regards,
> >
> > Maria
> >
> > _______________________________________________
> > USRP-users mailing list
> > USRP-users@lists.ettus.com
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> >
>
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