https://bugs.freedesktop.org/show_bug.cgi?id=82253
Michel Dänzer changed:
What|Removed |Added
Assignee|dri-devel@lists.freedesktop |mesa-dev@lists.freedesktop.
From: Michel Dänzer
Prevents logs from getting spammed with BO allocation failure messages.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82162
Signed-off-by: Michel Dänzer
---
src/gallium/drivers/radeon/r600_texture.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/
What IR? A flatland GLSL IR? A replacement for Mesa IR? Something else?
It's more of a question of which gallium hardware drivers are going to
support it. I don't think there will be any eager candidates.
The D3D9 state tracker already converts predicates to IFs.
Marek
On Thu, Aug 7, 2014 at 2:
On Wed, Aug 6, 2014 at 9:27 AM, Neil Roberts wrote:
> Here is a v2 of the BPTC texture compression series. The main
> difference is that instead of going via DXT3 for the UNORM formats it
> now always uses the custom naïve compressor for all formats. This
> doesn't give very good-looking results b
Am 07.08.2014 00:10, schrieb Eric Anholt:
> Roland Scheidegger writes:
>
>> Am 06.08.2014 22:33, schrieb Eric Anholt:
>
>>> + * When building using the simulator (on x86), we advertise ourselves as
>>> the
>>> + * i965 driver so that you can just make a directory with a link from
>>> + * i965_d
Carl Worth writes:
> It probably wouldn't be too hard to fix this code to be more general. I
> might take a whack at that now that I have this test in hand.
It wasn't too hard. I just sent a v2 patch in reply to the original (and
also force-pushed a new glcpp-fixup branch to my repository).
I've
Sometimes the newline separator is a single character, and sometimes it is two
characters. Before we can fold away and line-continuation backslashes, we
identify the flavor of line separator that is in use.
With this identified, we then correctly search for backslashes followed
immediately by the
On Wed, Aug 6, 2014 at 5:10 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> Neved used.
> ---
Connor's new IR has predication. You may not want to remove this quite yet.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.o
On 06/08/14 21:33, Eric Anholt wrote:
I'd like to start merging the VC4 driver. I've got a lot of things
working under sim (piglit's at 5212/6726 for a slightly-trimmed
quick.py), and once I find where I put my serial cable I hope to get the
kernel fixed up and passing even more than that on HW.
From: Marek Olšák
Neved used.
---
src/gallium/auxiliary/gallivm/lp_bld_limits.h | 4 -
src/gallium/auxiliary/gallivm/lp_bld_tgsi.h| 2 -
src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c| 46 ---
src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c | 6 +-
src/gallium/aux
Ian Romanick writes:
> Are the preprocessor patches on the gles3conform-v4 branch of my fd.o
> repo the most up to date?
Yes. The state of those patches matches what I have on my branch, (at
least as far as GLES3 conformance is concerned---I have some subsequent
preprocessor patches which shouldn
I think OpenVMS was the only platform that Mesa ran on that used a
non-IEEE representation for floats. We removed OpenVMS support a while
back, and this should alleviate the need to continue updating the
this-platform-uses-IEEE list.
The one bit of this patch that needs review is the IS_INF_OR_NAN
Am 07.08.2014 00:32, schrieb Ilia Mirkin:
> On Wed, Aug 6, 2014 at 6:06 PM, Marek Olšák wrote:
>> From: Marek Olšák
>>
>> This limit is fixed in Mesa core and cannot be changed.
>> It only affects ARB_vertex_program and ARB_fragment_program.
>>
>> The minimum value for ARB_vertex_program is 1 acc
https://bugs.freedesktop.org/show_bug.cgi?id=82268
Matt Turner changed:
What|Removed |Added
Status|NEW |ASSIGNED
--- Comment #1 from Matt Turner
On Thu, Aug 7, 2014 at 12:32 AM, Ilia Mirkin wrote:
> On Wed, Aug 6, 2014 at 6:06 PM, Marek Olšák wrote:
>> From: Marek Olšák
>>
>> This limit is fixed in Mesa core and cannot be changed.
>> It only affects ARB_vertex_program and ARB_fragment_program.
>>
>> The minimum value for ARB_vertex_progr
There's extensions like NV_vertex_program2 which can make use of more
than one address reg, I guess that's the reason why it was in gallium
(this extension also comes with opcodes arr,ara for instance which are
in gallium too).
But I doubt anyone plans to implement that so this should be fine.
Inte
On Wed, Aug 6, 2014 at 6:06 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> This limit is fixed in Mesa core and cannot be changed.
> It only affects ARB_vertex_program and ARB_fragment_program.
>
> The minimum value for ARB_vertex_program is 1 according to the spec.
> The maximum value for ARB_ve
Hey Carl.
Are the preprocessor patches on the gles3conform-v4 branch of my fd.o
repo the most up to date? I seem to have lost the patches from my
inbox. :( I've put R-b on almost all of them.
I want to look a little closer at "glsl/glcpp: Fix for macros that
expand to include "defined" operator
https://bugs.freedesktop.org/show_bug.cgi?id=82268
Priority: medium
Bug ID: 82268
Assignee: mesa-dev@lists.freedesktop.org
Summary: Add support for the OpenRISC architecture (or1k)
Severity: enhancement
Classification: Unclassified
Roland Scheidegger writes:
> Am 06.08.2014 22:33, schrieb Eric Anholt:
>> + * When building using the simulator (on x86), we advertise ourselves as the
>> + * i965 driver so that you can just make a directory with a link from
>> + * i965_dri.so to the built vc4_dri.so, and point LIBGL_DRIVERS_PA
From: Marek Olšák
This limit is fixed in Mesa core and cannot be changed.
It only affects ARB_vertex_program and ARB_fragment_program.
The minimum value for ARB_vertex_program is 1 according to the spec.
The maximum value for ARB_vertex_program is limited to 1 by Mesa core.
The value should be
On Wed, Aug 6, 2014 at 11:19 AM, Matt Turner wrote:
> On Tue, Aug 5, 2014 at 10:21 AM, Pohjolainen, Topi
> wrote:
>> On Thu, Jul 24, 2014 at 07:54:15PM -0700, Matt Turner wrote:
>>> ---
>>> src/mesa/drivers/dri/i965/brw_cfg.cpp | 24
>>> src/mesa/drivers/dri/i965/brw_cfg
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_query.c | 14 ++
src/gallium/drivers/radeon/r600_streamout.c | 9 +++--
src/gallium/drivers/radeon/r600_texture.c | 12 +---
3 files changed, 14 insertions(+), 21 deletions(-)
diff --git a/src/gallium/drivers/r
From: Marek Olšák
R600-R700 don't support virtual memory.
---
src/gallium/drivers/r600/r600_state.c | 27 +--
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 258ffd1..607b1
From: Marek Olšák
---
src/gallium/drivers/r600/evergreen_compute.c| 5 +--
src/gallium/drivers/r600/evergreen_hw_context.c | 6 ++--
src/gallium/drivers/r600/evergreen_state.c | 47 +++--
src/gallium/drivers/r600/r600_hw_context.c | 4 +--
src/gallium/drivers
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_cs.h | 9 -
1 file changed, 9 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_cs.h
b/src/gallium/drivers/radeon/r600_cs.h
index b30b465..3cee760 100644
--- a/src/gallium/drivers/radeon/r600_cs.h
+++ b/src/gallium/drivers/r
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_compute.c | 10
src/gallium/drivers/radeonsi/si_descriptors.c | 33 ---
src/gallium/drivers/radeonsi/si_dma.c | 12 +-
src/gallium/drivers/radeonsi/si_hw_context.c | 2 +-
src/gallium/dri
From: Marek Olšák
This will help to get rid of the buffer_get_virtual_address calls.
---
src/gallium/drivers/radeon/r600_buffer_common.c | 7 +--
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeon/r600_texture.c | 1 +
3 files changed, 7 insertions(+), 2
On Wed, Aug 6, 2014 at 10:31 AM, Jason Ekstrand wrote:
> Signed-off-by: Jason Ekstrand
> ---
> src/mesa/main/formats.csv | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/formats.csv b/src/mesa/main/formats.csv
> index f45e34b..eade6fa 100644
> --- a/src/mesa
Future commits add implicit parameters so
we can no longer rely on shader param size
Signed-off-by: Jan Vesely
---
src/gallium/drivers/ilo/ilo_gpgpu.c | 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 4 +--
src
This respin includes Francisco's approach of providing implicit
in the arg vector passed from clover, and Tom's idea of appending
implicit args after the kernel args.
I assumed it's not safe to modify exec.input, so the input vector is copied
before appending work dim.
Passes get-work-dim piglit
Signed-off-by: Jan Vesely
---
src/gallium/drivers/r600/evergreen_compute.c | 14 --
src/gallium/drivers/r600/evergreen_compute.h | 1 -
src/gallium/drivers/radeonsi/si_compute.c| 6 +++---
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/r600/
Signed-off-by: Jan Vesely
---
src/gallium/state_trackers/clover/core/kernel.cpp | 162 --
1 file changed, 85 insertions(+), 77 deletions(-)
diff --git a/src/gallium/state_trackers/clover/core/kernel.cpp
b/src/gallium/state_trackers/clover/core/kernel.cpp
index 68e91d5..7a88d
Am 06.08.2014 22:33, schrieb Eric Anholt:
> I'd like to start merging the VC4 driver. I've got a lot of things
> working under sim (piglit's at 5212/6726 for a slightly-trimmed
> quick.py), and once I find where I put my serial cable I hope to get the
> kernel fixed up and passing even more than t
OK, assuming no one complains, I'll push the series later today.
On Thu, Aug 7, 2014 at 8:44 AM, Ian Romanick wrote:
> On 08/06/2014 12:40 PM, Chris Forbes wrote:
>> Yes -- there's no interaction between patches 3 and 4. Blorp only
>> shares the generator.
>
> Okay. Then these two are also
>
> R
ville.syrj...@linux.intel.com writes:
> From: Ville Syrjälä
>
> Gen2 doesn't have fragmnts shaders so we shouldn't be calling
spelling^
Other than that, patches 4-9 are:
Reviewed-by: Eric Anholt
pgp3isQE9B0y5.pgp
Description: PGP signature
___
On 08/06/2014 12:40 PM, Chris Forbes wrote:
> Yes -- there's no interaction between patches 3 and 4. Blorp only
> shares the generator.
Okay. Then these two are also
Reviewed-by: Ian Romanick
> On Tue, Aug 5, 2014 at 1:32 PM, Ian Romanick wrote:
>> Does it still build with patch 3 without pat
ville.syrj...@linux.intel.com writes:
> From: Ville Syrjälä
>
> Gen2 doesn't support the A8 texture format. Currently the driver
> substitutes it with I8, but that results in incorrect RGB values.
> Use A8L8 instead. We end up wasting a bit of memory, but at least
> we should get the correct resu
I'd like to start merging the VC4 driver. I've got a lot of things
working under sim (piglit's at 5212/6726 for a slightly-trimmed
quick.py), and once I find where I put my serial cable I hope to get the
kernel fixed up and passing even more than that on HW.
I'm at 80 commits right now, with 3 in
Does this actually work on all Gen7?
The IVB PRM Vol 4 Part 1 Page 83 says:
Errata: BC6H_SF16, BC6H_UF16, and BC7_SRGB are not supported and
may result in data corruption if used.
On Thu, Aug 7, 2014 at 4:27 AM, Neil Roberts wrote:
> Here is a v2 of the BPTC texture compression series. The m
Yes -- there's no interaction between patches 3 and 4. Blorp only
shares the generator.
On Tue, Aug 5, 2014 at 1:32 PM, Ian Romanick wrote:
> Does it still build with patch 3 without patch 4?
>
> On 08/04/2014 01:58 AM, Chris Forbes wrote:
>> Signed-off-by: Chris Forbes
>> ---
>> src/mesa/drive
On Wed, Aug 6, 2014 at 9:50 AM, Neil Roberts wrote:
> I'd just liked to point out that I made a nearly identical patch before
> this patch was posted but I didn't get any review despite prodding
> people a few times on #dri-devel. Maybe we should try to get into the
> habit of searching patchwork
From: Ville Syrjälä
The spec says using DOT4 for alpha is undefined unless DOT4 is also used
for color. It seems to do the right thing anyway, but better safe than sorry.
Also override numAlphaArgs to 2 for DOT4 since that's what it wants.
This migth fix something in case the specified alpha mod
From: Ville Syrjälä
gen2 doesn't supporte linear mip filter with anisotropic min/mag
filtering. The hardware would automagically downgrade the min/mag
filters to linear in such cases, which IMO looks worse than forcing
the mip filter to nearest.
Signed-off-by: Ville Syrjälä
---
src/mesa/driver
From: Ville Syrjälä
TEXTURE_SET() is the only register macro that forgets to wrap the
argument evaluation in parens. Only simple integers are passed to this
macro so there's no bug but sitll it seems prudent to add the
parens.
Signed-off-by: Ville Syrjälä
---
src/mesa/drivers/dri/i915/i830_reg
From: Ville Syrjälä
Gen2 doesn't have fragmnts shaders so we shouldn't be calling
_mesa_meta_glsl_Clear() on gen2. Restore the appropriate
ARB_fragment_shader check to the clear path which was lost in:
commit 94f22fbe787214580a1a13a774114d2650c166cb
Author: Tapani Pälli
Date: Wed Aug 8 20:
From: Ville Syrjälä
According to gen2 BSpec the pipeline must be flushed at least up to the
windower before changing the scissor rect enable field. Emitting the
3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE is sufficient
to do that.
gen3 BSpec no longer has that piece of text, but le
From: Ville Syrjälä
ctx.hw_stencil is not used anywhere so kill it.
Signed-off-by: Ville Syrjälä
---
src/mesa/drivers/dri/i915/intel_context.c | 1 -
src/mesa/drivers/dri/i915/intel_context.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/intel_context.c
b/src/
From: Ville Syrjälä
Gen2 doesn't support depth/stencil textures, and since
commit c1d4d4999303f9167b20f4e0674b9436e6295cf7
Author: Ville Syrjälä
Date: Thu Apr 24 14:11:43 2014 +0300
i915: Don't advertise Z formats in TextureFormatSupported on gen2
depth/stencil formats are no longer
From: Ville Syrjälä
Check that the target is GL_TEXTURE_CUBE_MAP before emitting
TEXCOORDTYPE_VECTOR texture coordinates.
I'm not sure if the hardware would like CARTESIAN coordinates
with cube maps, and as I'm too lazy to find out just emit the
VECTOR coordinates for cube maps always. For other
From: Ville Syrjälä
Gen2 doesn't support the A8 texture format. Currently the driver
substitutes it with I8, but that results in incorrect RGB values.
Use A8L8 instead. We end up wasting a bit of memory, but at least
we should get the correct results.
Bugzilla: https://bugs.freedesktop.org/show_
From: Ville Syrjälä
I had a few rainy days during my summer vacation so I decided to fix a
chromnium-bsu texturing problem that was nagging me for a while now. I
ended up fixing a few other things too that I spotted mostly from reading
the code.
The aniso vs. mip filter thing probably comes down
On Wed, Aug 6, 2014 at 5:22 AM, Pohjolainen, Topi
wrote:
> On Tue, Aug 05, 2014 at 09:14:55PM +0300, Pohjolainen, Topi wrote:
>> On Thu, Jul 24, 2014 at 07:54:12PM -0700, Matt Turner wrote:
>> > ---
>> > src/mesa/drivers/dri/i965/brw_cfg.h | 8
>> > 1 file changed, 8 insertions(+)
>> >
>
On Tue, Aug 5, 2014 at 10:21 AM, Pohjolainen, Topi
wrote:
> On Thu, Jul 24, 2014 at 07:54:15PM -0700, Matt Turner wrote:
>> ---
>> src/mesa/drivers/dri/i965/brw_cfg.cpp | 24
>> src/mesa/drivers/dri/i965/brw_cfg.h | 2 ++
>> 2 files changed, 26 insertions(+)
>>
>> diff
FYI, it seems to be DrawPixels(GL_STENCIL_INDEX) that is broken. We
actually use S8 texturing for DrawPixels and some of the functions you
changed probably don't support S8 anymore.
Marek
On Wed, Aug 6, 2014 at 7:37 PM, Jason Ekstrand wrote:
> Michael,
> With the two patches I just sent to the l
Signed-off-by: Jason Ekstrand
---
src/mesa/main/formats.csv | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/formats.csv b/src/mesa/main/formats.csv
index f45e34b..eade6fa 100644
--- a/src/mesa/main/formats.csv
+++ b/src/mesa/main/formats.csv
@@ -279,4 +279,4 @@ M
Michael,
With the two patches I just sent to the list, the generated format_info
structure is now binary-identical to the original structure commited to git
with the following two exceptions: The string name parameter for
MESA_FORMAT_R9G9B9E5_FLOAT was updated from "MESA_FORMAT_RGB9_E5" to
"MESA_FO
Red-only formats should be x001 and RG formats should be xy01.
Signed-off-by: Jason Ekstrand
---
src/mesa/main/formats.csv | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/formats.csv b/src/mesa/main/formats.csv
index 5abb706..f45e34b 100644
--- a/src/mes
Michael,
Could you please point me at the failing tests. I don't have a radeon, but
I can run with llvmpipe or dri swrast and try to find the bug that way.
--Jason Ekstrand
On Wed, Aug 6, 2014 at 2:36 AM, Michel Dänzer wrote:
> On 06.08.2014 18:28, Michel Dänzer wrote:
> > On 06.08.2014 03:08,
Sorry, said that just a little early. Do we really want 4 bits for a
floating-point format? How many bits does nvidia report?
--Jason
On Wed, Aug 6, 2014 at 9:55 AM, Jason Ekstrand wrote:
> This looks fine to me.
> Reviewed-by: Jason Ekstrand
>
>
> On Wed, Aug 6, 2014 at 9:27 AM, Neil Robert
Looks fine
Reviewed-by: Jason Ekstrand
On Wed, Aug 6, 2014 at 9:27 AM, Neil Roberts wrote:
> If the name of a compressed texture format has ‘FLOAT’ in it it will now
> set
> the data type of the format to GL_FLOAT. This will be needed for the BPTC
> half-float formats.
> ---
> src/mesa/main/f
This looks fine to me.
Reviewed-by: Jason Ekstrand
On Wed, Aug 6, 2014 at 9:27 AM, Neil Roberts wrote:
> Adds the ‘bptc’ layout to get_channel_bits. The channel bits for BPTC
> depend
> on the mode but as it only has to be an approximation we can set it to 4
> like
> for S3TC.
> ---
> src/mes
I'd just liked to point out that I made a nearly identical patch before
this patch was posted but I didn't get any review despite prodding
people a few times on #dri-devel. Maybe we should try to get into the
habit of searching patchwork for existing patches before posting to the
list. Does anyone
Previously the Meta implementation of glGetTexImage would fall back to
_mesa_get_teximage if the texturing is not using an unsigned normalised
format. However in order to support the half-float formats of BPTC textures we
can make it render to a floating-point renderbuffer instead. This patch makes
This adds compressors for all four of the BPTC compressed-texture formats. The
compressor is written from scratch and takes a very simple approach. It always
uses a single mode of the BPTC format (4 for unorm and 3 for half-floats) and
picks the two endpoints by dividing the texels into those which
Enables the BPTC extension on Gen>=7 and adds the necessary format mappings to
get the right surface type value.
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 5 +
src/mesa/drivers/dri/i965/intel_extensions.c| 2 ++
2 files changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dr
---
docs/GL3.txt| 2 +-
docs/relnotes/10.3.html | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index e241257..973495c 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -138,7 +138,7 @@ GL 4.1:
GL 4.2:
GLSL 4.2
The signed and unsigned half-float BPTC-compressed formats were being reported
as having a base format of GL_RGBA but they don't store an alpha channel so it
should be GL_RGB.
---
src/mesa/main/texcompress.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/texc
Adds functions to fetch from any of the four BPTC-compressed formats.
v2: Set the alpha component to 1.0 when fetching from the half-float formats
instead of leaving it uninitialised. Don't linearize the alpha component
when fetching from sRGB.
---
src/mesa/Makefile.sources| 1 +
Once we add BPTC texture support we will need to generate mipmaps for
compressed floating point textures too. Most of the code seems to already be
there but it just needs a few extra lines to get it to use GL_FLOAT instead of
GL_UNSIGNED_BYTE as the type for the temporary buffers.
---
src/mesa/mai
Here is a v2 of the BPTC texture compression series. The main
difference is that instead of going via DXT3 for the UNORM formats it
now always uses the custom naïve compressor for all formats. This
doesn't give very good-looking results but it is fast and doesn't add
any dependencies. There was som
Enables BPTC texture compression on the software rasterizer.
---
src/mesa/main/extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index f3197f9..7732249 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@
If the name of a compressed texture format has ‘FLOAT’ in it it will now set
the data type of the format to GL_FLOAT. This will be needed for the BPTC
half-float formats.
---
src/mesa/main/format_info.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/format_in
This adds the following four Mesa image format enums which correspond to the
four BPTC compressed texture formats:
MESA_FORMAT_BPTC_RGBA_UNORM
MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM
MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT
MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT
It also updates the format information functio
Adds the ‘bptc’ layout to get_channel_bits. The channel bits for BPTC depend
on the mode but as it only has to be an approximation we can set it to 4 like
for S3TC.
---
src/mesa/main/format_info.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/format_info.py b/s
This adds a boolean in the gl_extensions struct for
GL_ARB_texture_compression_bptc as well as an entry in extension_table.
---
src/mesa/main/extensions.c | 1 +
src/mesa/main/mtypes.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
On Mon, Aug 4, 2014 at 6:48 AM, Andreas Boll wrote:
> The initial firmware for hawaii does not support type3 nop packet.
> Detect the new hawaii firmware with query RADEON_INFO_ACCEL_WORKING2.
> If the returned value is 3, then the new firmware is used.
>
> This patch uses type2 for the old firmwa
On Wed, Aug 6, 2014 at 5:53 PM, Ilia Mirkin wrote:
> pc->MaxAddressRegs = pc->MaxNativeAddressRegs =
> _min(screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_MAX_ADDRS),
> MAX_PROGRAM_ADDRESS_REGS);
>
> Not really sure what that's referring to... ARB_vp/fp o
pc->MaxAddressRegs = pc->MaxNativeAddressRegs =
_min(screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_MAX_ADDRS),
MAX_PROGRAM_ADDRESS_REGS);
Not really sure what that's referring to... ARB_vp/fp or something?
Anyways, this is definitely a bit of a violatio
On Wed, Aug 6, 2014 at 11:30 AM, Marek Olšák wrote:
> On Wed, Aug 6, 2014 at 4:01 PM, Alex Deucher wrote:
>> On Wed, Aug 6, 2014 at 9:32 AM, Marek Olšák wrote:
>>> From: Marek Olšák
>>>
>>> The code is rewritten to take known constraints into account, while always
>>> using 0 by default.
>>>
>>
I guess PIPE_SHADER_CAP_MAX_ADDRS is now useless, because it can be
derived from GLSL_FEATURE_LEVEL, right?
Marek
On Wed, Aug 6, 2014 at 5:25 PM, Ilia Mirkin wrote:
> Replace the plain sampler index with a register reference to a sampler.
> We also need to keep track of the sampler array size wh
On Wed, Aug 6, 2014 at 4:01 PM, Alex Deucher wrote:
> On Wed, Aug 6, 2014 at 9:32 AM, Marek Olšák wrote:
>> From: Marek Olšák
>>
>> The code is rewritten to take known constraints into account, while always
>> using 0 by default.
>>
>> This should improve performance for multi-SE parts in theory
Am 06.08.2014 17:20, schrieb Ilia Mirkin:
> On Wed, Aug 6, 2014 at 11:15 AM, Roland Scheidegger
> wrote:
>> Am 06.08.2014 17:03, schrieb Ilia Mirkin:
>>> On Wed, Aug 6, 2014 at 10:52 AM, Roland Scheidegger
>>> wrote:
Am 06.08.2014 13:00, schrieb Marek Olšák:
> On Wed, Aug 6, 2014 at 4:
Replace the plain sampler index with a register reference to a sampler.
We also need to keep track of the sampler array size when there is a
relative reference so that we can mark the whole array used.
To facilitate implementation, we add a separate ADDR register that
exclusively handles the sampl
On Wed, Aug 6, 2014 at 11:15 AM, Roland Scheidegger wrote:
> Am 06.08.2014 17:03, schrieb Ilia Mirkin:
>> On Wed, Aug 6, 2014 at 10:52 AM, Roland Scheidegger
>> wrote:
>>> Am 06.08.2014 13:00, schrieb Marek Olšák:
On Wed, Aug 6, 2014 at 4:02 AM, Ilia Mirkin wrote:
> On Tue, Aug 5, 2014
Am 06.08.2014 17:03, schrieb Ilia Mirkin:
> On Wed, Aug 6, 2014 at 10:52 AM, Roland Scheidegger
> wrote:
>> Am 06.08.2014 13:00, schrieb Marek Olšák:
>>> On Wed, Aug 6, 2014 at 4:02 AM, Ilia Mirkin wrote:
On Tue, Aug 5, 2014 at 5:25 PM, Roland Scheidegger
wrote:
> From a gallium
On Wed, Aug 6, 2014 at 9:33 AM, Marek Olšák wrote:
> From: Marek Olšák
>
> If the driver crashes in create_xx_shader, you want to see the shader.
Reviewed-by: Ilia Mirkin
> ---
> src/mesa/state_tracker/st_program.c | 22 ++
> 1 file changed, 10 insertions(+), 12 deletions(
On Wed, Aug 6, 2014 at 10:52 AM, Roland Scheidegger wrote:
> Am 06.08.2014 13:00, schrieb Marek Olšák:
>> On Wed, Aug 6, 2014 at 4:02 AM, Ilia Mirkin wrote:
>>> On Tue, Aug 5, 2014 at 5:25 PM, Roland Scheidegger
>>> wrote:
From a gallium perspective, indirect temp regs are already working
Am 06.08.2014 13:00, schrieb Marek Olšák:
> On Wed, Aug 6, 2014 at 4:02 AM, Ilia Mirkin wrote:
>> On Tue, Aug 5, 2014 at 5:25 PM, Roland Scheidegger
>> wrote:
>>> From a gallium perspective, indirect temp regs are already working - so
>>> something like
>>> MOV TEMP[0], TEMP[TEMP[1].x] should wo
On 07/30/2014 04:11 AM, Tapani Pälli wrote:
> Current version can create ir_expression where operands have
> different base type, patch adds support for unsigned type.
>
> Signed-off-by: Tapani Pälli
> https://bugs.freedesktop.org/show_bug.cgi?id=80880
> ---
> src/glsl/loop_controls.cpp | 18 +++
On Aug 5, 2014, at 9:40 PM, srol...@vmware.com wrote:
> From: Roland Scheidegger
>
> If the vertex shader has no position but the gs has, the clipvertex output
> was -1 (because it's the same as vs position in this case if there's no
> explicit clipvertex output). This caused crashes (or assertio
On Wed, Aug 6, 2014 at 9:32 AM, Marek Olšák wrote:
> From: Marek Olšák
>
> This isn't documented anywhere, but it's the only thing that works
> for this case.
Reviewed-by: Alex Deucher
> ---
> src/gallium/drivers/radeonsi/si_state_draw.c | 7 ++-
> 1 file changed, 2 insertions(+), 5 dele
On Wed, Aug 6, 2014 at 9:32 AM, Marek Olšák wrote:
> From: Marek Olšák
>
> The code is rewritten to take known constraints into account, while always
> using 0 by default.
>
> This should improve performance for multi-SE parts in theory.
>
> A debug option is also added for easier debugging. (If
On Wed, Aug 6, 2014 at 9:28 AM, Marek Olšák wrote:
> From: Marek Olšák
>
> This validates all bound buffers (CB, ZB, textures, DMA) at the beginning
> of CS. This fixes "bo->space_accouned" assertion failures.
>
> Tested by: Jochen Rollwagen
> Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by:
On 08/05/2014 10:35 AM, Roland Scheidegger wrote:
Am 30.07.2014 19:08, schrieb Brian Paul:
Compute the bitmask of supported array types once instead of every
time we call a GL vertex array function.
---
src/mesa/main/mtypes.h |3 ++
src/mesa/main/varray.c | 86 ++
From: Marek Olšák
This isn't documented anywhere, but it's the only thing that works
for this case.
---
src/gallium/drivers/radeonsi/si_state_draw.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/rade
From: Marek Olšák
The code is rewritten to take known constraints into account, while always
using 0 by default.
This should improve performance for multi-SE parts in theory.
A debug option is also added for easier debugging. (If there are hangs,
use the option. If the hangs go away, you have f
From: Marek Olšák
If the driver crashes in create_xx_shader, you want to see the shader.
---
src/mesa/state_tracker/st_program.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/src/mesa/state_tracker/st_program.c
b/src/mesa/state_tracker/st_program.c
From: Marek Olšák
This validates all bound buffers (CB, ZB, textures, DMA) at the beginning
of CS. This fixes "bo->space_accouned" assertion failures.
Tested by: Jochen Rollwagen
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/r200/r200_context.c| 1 +
src/mesa/driv
2014-08-04 21:25 GMT+02:00 Eric Anholt :
> thomashellan...@gmail.com writes:
>
>> From: Thomas Helland
>>
>> When writing that A || (A && B) patch some
>> days ago I also wrote some other patches
>> that have no impact on my collection of shaders.
>> (shader-db + Some TF2 and Portal-shaders).
>> N
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