f
guest of simulate,but
i don't know "pmemAddr" is used to do.
Can anyone please help me to understand this?
I would guess that pmemAddr means "physical memory address", but I can't say
precisely what it means
in this context. I would look for how it is initialized
e stack region into the cache.
Regards - Eliot Moss
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-) ...
If I have my gem5 understanding wrong, I am happy to be corrected
by someone who knows more!
Regards - Eliot Moss
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are repeatable, you
can set a conditional breakpoint at the place where the packet is created, or
other places along the path of its processing, and possibly find where things
go off the rails.
Regards - Eliot Moss
>
---
On 7/14/2022 2:46 PM, Abdlerhman Abotaleb wrote:
Thank you, Eliot, for your reply. 🙏
I solved it, but still need to understand the cause. *
*
*This is the full story: *
I defined an STL queue of pointers to Packets to store the packets for further
resending.
std::queue pktQueue;
It is defined as
On 7/14/2022 8:07 PM, Abdlerhman Abotaleb wrote:
Thanks Eliot for the follow up.
The reposne is created independently using the memory controller.
and the problem arises inside recvTimingReq, so it happens even before complete
sending teh request.
I don't free up the pkt pointer "pkt", I pop th
On 7/15/2022 7:54 AM, Abdlerhman Abotaleb wrote:
> But in such case, GEM5 code will fail without my memory object being added
and this is not the case,
> it was working perfectly.
> Because, omitting the added simulation object, the packet pointer "pkt" is
being sent to the
> crossbar then the m
On 9/19/2022 10:04 PM, 2497597 wrote:
Hello！I‘m a college student and I need to do some work with garnet.
But I found a inexplicable problem recently.
Command to Run:
./build/NULL/gem5.opt
configs/example/garnet_synth_traffic.py \
--network=garnet \
--num-cpus=64 \
--num-dirs=64 \
--topology=Mes
or things, and even different stack alignment.
I have seen this in C / C++ programs before and it can be nasty to ferret out.
Best wishes - Eliot Moss
-- 原始邮件 --
*发件人:* "The gem5 Users mailing list" ;
*发送时间:* 2022年9月20日(星期二) 下午5:16
*收件人:* "gem5-users&quo
e OS boot process - 15 to 20 minutes on
reasonably fast x86 processors - and there are places in that
boot process where there is no output for quite some time.
Best - Eliot Moss
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On 9/26/2022 3:51 PM, Humza Ikram wrote:
I ran it again and it finished in a little under 3 hours.
Thank you for replying and clarifying.
Wow, that's long. You can see why it is helpful to do actual
runs starting from a checkpoint!
Regards - Eliot
.
I further observe that if we are talking about an
Intel processor. those processor handle loads in the
order the program presents them. Not sure if that
has any impact here. Also unsure whether cpu
speculative execution plays a role (which would actually
improve matters).
Best - Eliot Moss
On
On 10/7/2022 1:13 PM, Eliot Moss wrote:
On 10/7/2022 1:03 PM, Aritra Bagchi wrote:
Hi all,
Any suggestions on this are most helpful.
Thanks and regards,
Aritra
My guess is that it is because the non-unrolled loop
has a test of i against 1000 before each access to A[i].
That test guards the
On 10/7/2022 1:30 PM, Aritra Bagchi wrote:
Hi Eliot,
Thanks for the response. The unrolled loop, despite having the same dependency across "j", can send
multiple loads simultaneously. So the limitation might not be due to that dependency across "j" of
different iterations. But in the non-unrol
code, but that later cache accesses caused a replacement and the
block's information changed accordingly. I suspect that if you
want stable information, you will need to copy the block.
Regards - Eliot Moss
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the decoding of all of this
to determine _where_ I need to make a code change ...
Regards, and thanks in advance -- Eliot Moss
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On 6/7/2019 5:06 AM, Nikos Nikoleris wrote:
Hi Eliot,
gem5 already implements the AArch32 [1] and AArch64 [2] data cache
maintenance instructions by VA. Can you use these, or do you need to add
some custom functionality?
[1]:
https://github.com/gem5/gem5/commit/eeb36e5b6e81c6b9ea6a0c3c97573e762
On 6/7/2019 8:56 AM, Nikos Nikoleris wrote:
On 07/06/2019 13:40, Eliot Moss wrote:
On 6/7/2019 5:06 AM, Nikos Nikoleris wrote:
Hi Eliot,
gem5 already implements the AArch32 [1] and AArch64 [2] data cache
maintenance instructions by VA. Can you use these, or do you need to add
some custom
or is from a library? You might need to get a different
version of some library that it's linking with ...Eliot Moss
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rt. Still, I admit I am not familiar with the
low-level scheduling "guts" of Gem5, which is a key part that would need to
change. However, to do well, one would need to know how different components
depend on various pieces of state in order to determine what might run in
parallel, etc.
ence/snooping really works. Any thoughts
would be appreciated. As it stands, I am having to do more explicit cache
flushing / invalidating than I would like, but it seems reasonable that a
piece of hardware could work the way I envision.
Regards - Eliot Moss
__
need all the files, libraries, etc., on the simulated disk. I would not
think that static compilation is necessary if all the right libraries are in the
right places ...
Eliot Moss
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ne to go to S state in both caches. So the answer is *no*, if we're
talking about the same address space or a shared-memory page.
Other protocols might be out there, but I think this is pretty standard.
Eliot Moss
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ded libraries).
If the things you need are suitably added to an OS image, then you should be
able for up and run things.
Other folks may be able to point you are more detailed information on how to
add source code, byte code, and packages to an image prior to
so did not turn up anything.
What am I missing? :-)
Regards - Eliot Moss
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Never mind - found that it was some external script doing a 'tee'.
Sorry to waste bandwidth ... EM
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On 4/15/2020 1:13 PM, 周泰宇 wrote:
I don’t know why the format so garbled. So I post my code again.
|BaseCache::recvTimingReq(pkt){ wb_pkts.clear(); dirty_blk_count = my_memWriteback(wb_pkts); bool
satisfied = false; { PacketList writebacks; satisfied = access(pkt, blk, lat, writebacks); . }
On 12/28/2012 10:00 AM, Hossein Nikoonia wrote:
Or you can use more swap!
... and wait for days while paging. Truly, I found it
much easier to build on a machine with adequate RAM for
the task ...Eliot Moss
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find the
.hh file(s). This seem to be something about CPATH or its
equivalent, but not being an scons hacker, etc., I don't really
know what to do. I can provide more output if you like.
Regards -- Eliot Moss
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On 12/17/2011 6:06 PM, Steve Reinhardt wrote:
Hi Eliot,
We don't really support Cygwin anymore, at least not as a first-class platform.
We used to (a long
time ago), but it always had caveats and got ever more awkward. Meanwhile,
with all the free
virtualization products out now, it made mor
tiple executions of the same instruction ...
Eliot Moss
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-- Eliot Moss
Running test in
build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-atomic.
build/ALPHA_SE/gem5.debug -d build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-atomic
-re tests/run.py build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-atomic
I've seen in the message archives a note about EioProcess,
which I can ignore since it comes from the "encumbered"
package. But the other error is slightly concerning ...
Eliot
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Ok. I moved to gcc 4.4., using CC=gcc44 CXX=g++44 in the
scons command line. I stil get the funky thing about
$self from event.i. I removed the $ from those in event.i
and that part builds find. There is a line in pyrun.swg
in the swig I have installed that fails to put a (char*)
before "__dic
On 12/28/2011 3:53 PM, Steve Reinhardt wrote:
I noticed your swig version is also older than what's recommended... check the
link for details, as
it's a bit complicated. That's almost certainly the source of your $self
problem.
As for the memtest error, are you using the main gem5 code or gem
Ok, I found in the FAQ about using EXTRAS to
get EIO built in ... it almost worked to build,
but I had to copy two .h/.hh files over to the
build tree by hand.
But I get the same 6 failures, 5 EIO and 1 memtest.
For the EIO failures I ask: where is anagram? Do I
also need some set of benchmarks
On 12/29/2011 2:35 AM, Steve Reinhardt wrote:
I just updated my repository and ran these two commands:
scons -j 8 EXTRAS=../encumbered build/ALPHA_SE/tests/debug/quick
scons -j 8 build/ALPHA_SE/tests/opt/quick
and got no build errors and no test failures.
This was on our regression machine, so
raw newbie here, but my guess is that multithreaded
benchmarks require FS, not SE, builds of gem5
Eliot Moss
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d say you need to make
sure that -lpthread is the last of the libraries, or near the
last. You also need to make sure that it's on the linker's
search path (that is, that the directory containing libpthread.so
is on the search path).
This is all just ordinary C/C++ program compilation s
#x27;re linking statically,
it does not even need to be available at run time. Presumably
the features used by this library need to match well enough
those provided by the simulator (i.e., which syscalls).
Regards -- Eliot Moss
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gem5
rce that I failed to find.
Again, we are talking:
ARM, v8 (aarch64)
o3
full system
microarchitecture along the lines of A77 (plus or minus)
Thanks in advance -- Eliot Moss
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On 7/6/2021 12:42 PM, Eliot Moss via gem5-users wrote:
> Dear gem5-ers ...
>
> I am working on some full system simulations of ARM v8 that I hope to head
> toward publication, and thus would prefer to use processor and system
> configurations similar to recent offerings, say maybe
red things, or a C++ library bug. I am using
gcc 7.5.0 and libc.so.6. I will ttry a more recent compiler and
see what happens ...
Regards - Eliot Moss
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On 10/3/2021 2:34 PM, Eliot Moss via gem5-users wrote:
On 10/3/2021 1:43 PM, walt_90--- via gem5-users wrote:
I am seeing a similar fault. This is for gem5 21.0.0.0, for X86.
When trying to decode 0x1E in 64-bit mode, it tries to construct
a UD2 macroop (undefined instruction). Somewhere in
On 10/3/2021 7:03 PM, Eliot Moss via gem5-users wrote:
On 10/3/2021 2:34 PM, Eliot Moss via gem5-users wrote:
On 10/3/2021 1:43 PM, walt_90--- via gem5-users wrote:
I am seeing a similar fault. This is for gem5 21.0.0.0, for X86.
When trying to decode 0x1E in 64-bit mode, it tries to
On 10/4/2021 1:26 PM, Ali Ghandour via gem5-users wrote:
Hi Eliot,
I am having the same error.
1. I moved from gcc-9 t gcc-11 and the error still exists. So I am not sure if
it is really gcc related!
2. I printed the eventqDump() and I am trying to figure out if this can help debug the error
cmalloc reporting it.
fs.py has worked for me, maybe with some customizations.
I think that the wording about it is trying to suggest that
it's perhaps a bit rigid or limiting for things a lot of people
may want to do ...
Regards - Eliot Moss
__
On 10/5/2021 8:01 AM, Đức Anh wrote:
> Hi Eliot,
>
> How could you restore the checkpoint with fs.py? What command option did you
use? I read through the
> fs.py file so I believed m5.instatiate() is enough. I am using
> - gem5 version [DEVELOP-FOR-V21.2]
> - commit 6811158b28bd293487fb5e4bbbfb4b
eg() so
that it returns true for the physical register corresponding to the
architectural
zeroReg of any thread.
Regards - Eliot Moss
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%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
I have an external library that I would like to link with my gem5 build. How
do I do that? Also the code I want to compile that will use that library
needs to include a particular .h file. How do I work that into the build
process?
Thanks for tips on how to do this! Regards - Eliot Moss
weak to gem5. Things in that hierarchy are all virtual files
"faked up" by the kernel.
HTH - Eliot Moss
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On 2/17/2022 8:55 PM, Qaisar Bashir via gem5-users wrote:
Please remove my email
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READ t
the micro-op engine, my guess is that it's there for RISC-V as
well. A full fence wuold merely prevent issuing any ld/st ops until any ones
in progress are finished. Again, AFAICT, it's cpu thing, not a cache thing.
Best wishes - Eliot Moss
_
the caches for supporting
bulk cache operations like wbinv, I might be able to extract a
patch. It would be a bit of work because I also have stuff for
a different mechanism in there that is part of research maybe
toward a publication, so we're not quite ready to share that par
nication channel there. Still, by the time a context switch is complete,
those buffers may be guaranteed to have cleared - provided we can make an
argument that there is a fixed maximum amount of time needed for that to
happen.
Anyway, I hope this helps.
Eliot Moss
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gards - Eliot Moss
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et up? What cpu is DerivO3CPU roughly
modeled on? Other suggestions / guidance?
Regards - Eliot Moss
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Retrying this since I have not received a response ...
Thanks for your thoughts on the matter! Eliot
On 3/19/2022 7:23 PM, Eliot Moss via gem5-users wrote:
Dear gem5-ers --
I've been running an x86 DerivO3CPU pretty much as it comes, and now would
like to configure it to correspond we
like --defense to work, but at some point, some piece of code has to pass it
on to the actual component. A given component will ignore parameters that
do not match its name ...
Regards - Eliot Moss
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m the above.
HTH - Eliot Moss
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On 11/6/2022 3:36 PM, Eliot Moss via gem5-users wrote:
On 11/6/2022 3:17 PM, Sarthak Rout via gem5-users wrote:
Hello everyone,
I am trying to use MSR registers for experimenting on caches. I want to add a custom MSR to the
system which is simulated by Gem5 with Linux v5.4.84 kernel. I have
. it running through the whole OS boot procedure
that takes the 20 minutes +/- ...
Eliot Moss
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On 11/14/2022 12:42 AM, Hanhwi Jang via gem5-users wrote:
Thanks for your reply.
Yes. I mean that; serializing all SimObjects and writing them on a disk.
Does the checkpoint latency depend on the workload behavior?
For GCC, the checkpoint takes around 10 mins for a single point,' but it takes
3
In my experience, you need a checkpoint from an N cpu
system to restore in an N cpu system. That is, the
checkpoint contents depend on the number of cpus and
are not interchangeable. If I'm wrong about this,
I would be happy to be corrected!
Best wishes - Eliot
On 12/26/2022 9:24 AM, Eliot Moss via gem5-users wrote:
In my experience, you need a checkpoint from an N cpu
system to restore in an N cpu system. That is, the
checkpoint contents depend on the number of cpus and
are not interchangeable. If I'm wrong about this,
I would be happy
On 12/27/2022 2:48 AM, 李南松 wrote:
Hi Eliot Moss,
Thanks for your reply.
I am generating Checkpoint for SPEC2017. Do I need to regenerate my BBV
file under N cpus system?
There is a condition here that the simpoint_profile (BBV) cannot be generated
when n > 1.
$
I don't think you're "getting" my other points:
A checkpoint taken when running with N cpus **must** be restored on a system
running N cpus. This is inherent in the OS state and also in the fact that
the registers of N execution engines are saved / restored. Put another way,
the fact that N cpu
On 12/28/2022 4:09 AM, 李南松 via gem5-users wrote:
Hi EM,
I have found the root cause of this issue.
My multicore system didn't really work because I didn't modify the dtb
file.
So only one cpu is visible in my system /proc/cpuinfo file.
After recompiling the multi
d), I have not been able to find a way
to get at DynInstPtr referents when in gdb. Is there a trick to
printing / accessing fields of DynInst and StaticInst instances via
their respective Ptr types? The * and -> operator seem to be
unknown to gdb on those Ptr types.
Regards
On 1/3/2023 11:15 PM, Hoa Nguyen via gem5-users wrote:
I believe you can compile build/X86/gem5.debug to have all the symbols
available for debugging.
Yes, they are. I dont think that's the issue.
I'm not sure about the error, but generally, when debugging an instruction, I would try to fin
So, what I have found is that the bad micro-op is coming from trying to execute the micro-ops of an
INT3 macro-instruction. The end of the sequence consists of the micro-ops:
andi t0, t5, 0x1
br 0x803d
br 0x80b8
followed by a bunch of "panic" micro-ops. t5 holds an m5 register,
where the low
On 1/4/2023 11:51 PM, Eliot Moss via gem5-users wrote:
So, what I have found is that the bad micro-op is coming from trying to execute the micro-ops of an
INT3 macro-instruction. The end of the sequence consists of the micro-ops:
andi t0, t5, 0x1
br 0x803d
br 0x80b8
followed by a bunch of
On 1/6/2023 1:27 PM, Jason Lowe-Power via gem5-users wrote:
Hi Eliot,
Unfortunately, I don't have a direct answer for you. However, I want to say that I appreciate you
keeping the mailing list updated with your progress!
Thank you for the encouragement, Jason!
At this point I probably need t
ut do you want that compilation as part of your
measured workload? Something to think about.
Regards - Eliot Moss
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suggestion would be to make available also a new variable,
called (say) kernel_extra_args, that gets added rather than
replacing. That would be backward compatible and give strictly
additional functionality.
Regards - Eliot Moss
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rotected so you could not directly write it from user
mode.
I could not readily find any setting you can make to python model component
parameters to control this.
Regards - Eliot Moss
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On 2/9/2023 11:07 AM, Priyanka Ankolekar via gem5-users wrote:
Hello,
I am running RISCV in full system mode (configs/examples/riscv/fs_linux.py).
I would like to play with the configuration of caches, TLB etc.
I can see there are command line options to configure the i-cache, d-cache like
these
s best to start there when posting to a mailing list, since folks may
know quite different ways of getting at your objective ...
Best - Eliot Moss
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On 2/24/2023 11:31 AM, Priyanka Ankolekar via gem5-users wrote:
Hi Eliot,
I am trying to correlate my gem5 RISCV configuration with a RISCV RTL design
for a certain benchmark.
I would like to plot /retired instructions versus ticks/ to make sure that both (gem5 and RTL) are
(mostly) performing
more from
fundamentals would be helpful (channels, ranks, banks, devices, etc.).
Regards - Eliot Moss
PS: I've not forgotten about eventually contributing back cache cleaning
support. I did find that what had been built before was (at most) suitable
for clflush. It did not incorporate the looser
On 3/9/2023 3:01 PM, Eliot Moss via gem5-users wrote:
Dear gem5'ers - In my current simulation work it would be helpful to
understand better DRAM and NVM configuration. How do I determine, and how do
I set, the number of channels, interleaving, etc.? I'm far from being an
expert
solve this? Is there a solution other than implementing the
"palignr" instruction
I am using the last stable version of gem5 (v22.1, commit 5fa484e)
What comes to my mind is compiling while telling gcc to use an x86 model
that does not have the "offending" instruction.
B
On 3/9/2023 5:44 PM, Ayaz Akram wrote:
Hi Eliot,
gem5 splits the memory system modeling into two parts: 1) the memory controller and 2) the memory
interface. The memory interface can be a DRAMInterface or NVMInterface and provides many parameters
that are configured to achieve a specific memor
s its own logic.
Where you get separate directories is for different ISAs (x86 vs RISCV, for
example).
Cheers - Eliot Moss
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nning with emulated syscalls, though of
course it will tend to be a bit slower to simulate.
Regards - Eliot Moss
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me of the
valgrind tools, for example.
Others might be able to confirm or argue against my sense of the slowdown
factor (which I sometimes call the *time dilation* of simulation).
HTH - Eliot Moss
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On 3/13/2023 5:33 PM, Abitha Thyagarajan via gem5-users wrote:
Hi Eliot and Mirco,
I had the same issue with `palignr_Vdq_Wdq_Ib` being unimplemented. I tried compiling my application
binary (i.e., the one I was trying to run on gem5, not gem5 itself) to exclude SSE which contains
that instruc
, then "type python" will show you.
Cheers - Eliot Moss
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t maybe that was not intended?)
Regards - Eliot Moss
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On 3/18/2023 10:40 PM, Ayaz Akram via gem5-users wrote:
Hi Eliot,
MemCtrl() memory controller in gem5 can control a single DRAM interface or a single NVM interface at
a time. I think one way to verify that things are set-up correctly is to confirm this from the
"m5out/config.ini". If config.in
On 3/20/2023 5:05 PM, Priyanka Ankolekar via gem5-users wrote:
Hi Eliot,
(Picking this up again after a while.) :-)
Thank you for your detailed answer. I was able to get a lot of useful data
points from these statistics.
Is there a way to get what instruction was retired/committed and when (tic
little and tell
us what you're really trying to do, since neither the
retired instructions stats nor a full trace seem to meet
your need ...
Best - Eliot Moss
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On 3/22/2023 11:11 AM, Priyanka Ankolekar wrote:
Sorry, I should have clarified. I am using the RISCV ISA in gem5.
(As you could have done,) I checked the gem5 sources,
and it *does* model that register, returning totalInsts
as gem5 calculates that. Presumably that is the same as
statistics wi
On 3/22/2023 12:09 PM, Priyanka Ankolekar via gem5-users wrote:
Regarding the other part of your email:
Let me begin by saying I am a novice to both RISCV and gem5.
I have a RISCV RTL with a certain config. I have set up gem5 to match that configuration. I want to
make sure that they are indeed
think* I'm most interested in CXL.cache (giving a device
high performance coherent access to memory) and possibly
CXL.mem. I'm more interested in modeling the performance
than in modeling all the parameter read-out and setup that
would be in CXL.io, as I understand it.
Regar
do with how much of that memory is used
by the simulated application. Using grep over the source
code can help answer questions like this :-) ...
Regards - Eliot Moss
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an wind
backward and forward through an execution) to serve me well on
the C++ code.)
Best wishes - Eliot Moss
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ld at this point - Ubuntu bionic offers 10, for example.
Regards - Eliot Moss
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On 4/5/2023 1:25 PM, Ponda, Esha Ashish via gem5-users wrote:
I tried to look into it and found that my OS has libprotobuf17 installed
./build/ARM/gem5.opt configs/example/arm/starter_se.py --cpu="minor"
tests/test-progs/hello/bin/arm/linux/hello
I am trying to run the above command and get
their outputs (both the gem5 output
and the simulated program's output) to different files. When I
do this I also have some temporary mounts that I need to be
careful about so I copy the (fortunately small) different
mounted drive files.
Anyway, I do this all the time.
HTH --
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