Dear gem5'ers - In my current simulation work it would be helpful to understand better DRAM and NVM configuration. How do I determine, and how do I set, the number of channels, interleaving, etc.? I'm far from being an expert in memory devices / boards, so something that starts more from fundamentals would be helpful (channels, ranks, banks, devices, etc.).
Regards - Eliot Moss PS: I've not forgotten about eventually contributing back cache cleaning support. I did find that what had been built before was (at most) suitable for clflush. It did not incorporate the looser ordering rules for clflushopt and clwb, and of course if did not support the bulk cleaning operators (invd, wbinvd, wbnoinvd). I ended up enhancing LSQUnit to deal with the looser ordering (a subtle task), adding a separate cleanReqQueue in the caches (and determining what seems a reasonable priority between that, the MSHR queue and the writeback queue) and a bulk cleaning mechanism that involves the caches but also coherent xbars snoop "broadcasting" cleaning ops toward the the cpus, gathering back results, and counting writebacks to know when an op is truly finished. I'm giving some though as to how to break this into somewhat separable pieces - maybe: (1) proper ordering support and handling for clflushopt and clwb (and the stronger ordering of clflush); then (2) supporting the bulk clean operators. Suggestions on how to offer this back are welcome - it's a patch significant in size and I think hard to break into smaller pieces because of the way the pieces all need to play together. It's also hard to some up with little test cases other than programs with cleaning ops run with debug flags one to show what happened. Cheers - E _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
