On 10/10/2021 5:08 AM, saqi via gem5-users wrote:
Hi everyone, I want to implement simultaneous multithreading in FS mode in gem5. After modifying the number of threads according to SE mode, an error will be reported at run time. The error occurred in src / cpu / o3 / rename_map.cc, an assertion assert (prev_reg - > iszeroreg()) in the rename function. Commenting out the assertion will cause an idle run, and not doing so will terminate the run. The surrounding codes are as follows：SimpleRenameMap::rename(const RegId& arch_reg) { PhysRegIdPtr renamed_reg; // Record the current physical register that is renamed to the // requested architected register. PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()]; if (arch_reg == zeroReg) { assert(prev_reg->isZeroReg()); //!! renamed_reg = prev_reg; } else if (prev_reg->getNumPinnedWrites() > 0) { // Do not rename if the register is pinned assert(arch_reg.getNumPinnedWrites() == 0); // Prevent pinning the // same register twice DPRINTF(Rename, "Renaming pinned reg, numPinnedWrites %d\n", prev_reg->getNumPinnedWrites()); renamed_reg = prev_reg; renamed_reg->decrNumPinnedWrites(); } else { renamed_reg = freeList->getReg(); map[arch_reg.flatIndex()] = renamed_reg; renamed_reg->setNumPinnedWrites(arch_reg.getNumPinnedWrites()); renamed_reg->setNumPinnedWritesToComplete( arch_reg.getNumPinnedWrites() + 1); } What role does the assertion ** assert(prev_reg->isZeroReg()); ** in the register renaming function play in SMT? Why is there an error here? Looking forward to your reply!
I'm not familiar with the code, but here's an analysis that makes sense. If zeroReg is a register that always reads as zero, and to which no writes are allowed (or else they are ignored), then after renaming it will always be the same register. Put another way, if a register is read-only, then renaming will never create another version of it. When you added multi-threading, you probably introduced another physical register for zeroReg in the new thread. I think the solution is to adjust isZeroReg() so that it returns true for the physical register corresponding to the architectural zeroReg of any thread. Regards - Eliot Moss _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
