So, what I have found is that the bad micro-op is coming from trying to execute the micro-ops of an
INT3 macro-instruction. The end of the sequence consists of the micro-ops:
andi t0, t5, 0x1
br 0x803d
br 0x80b8
followed by a bunch of "panic" micro-ops. t5 holds an m5 register,
where the low bit supposedly indicated whether we are in long mode.
The br micro-ops branch into long sequences of micro-ops in the "ROM".
It would appear that somehow we are not doing what the br micro-ops
would do (presumably that andi is vectoring things?) but falling into
the panics.
Any thoughts on how to proceed with this?
Regards - Eliot
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